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DSM2150F5V
DSM (Digital Signal Processor System Memory) For Analog Devices DSPs (3.3V Supply)
FEATURES SUMMARY s Glueless Connection to DSP - Easily add memory, logic, and I/O to the External Port of ADSP-218x, 219x, 2106x, 2116x, 2153x, and TS101 families of DSPs from Analog Devices, Inc.
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- Create state machines, chip selects, simple shifters and counters, clock dividers, delays - Simple PSDsoft ExpressTM development software, free from www.st.com/psd Figure 1. Packages
Dual Flash Memories - Two independent Flash memory arrays for storing DSP code and data - Capable of read-while-write concurrent Flash memory operation - Device can be configured as 8-bit or 16-bit - Built-in programmable address decoding logic allows mapping individual sectors of each Flash array to any address boundary - Each Flash sector can be write protected
TQFP80 (T)
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512 KByte Main Flash memory - Ample storage for boot loading DSP code/ data upon reset and subsequent code swaps - Large capacity for storing tables and constants or for data recording In-System Programming (ISP) with JTAG - Program entire chip in 15-35 seconds with no involvement of the DSP - Optionally links with DSP JTAG debug port - Eliminate need for sockets and pre-programming of memory and logic devices - ISP allows efficient manufacturing and product testing supporting Just-In-Time inventory - Use low-cost FlashLINKTM cable with any PC. Available from www.st.com/psd.
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32 KByte Secondary Flash memory - Smaller sector size ideal for storing calibration and configuration constants. Eliminate external serial EEPROM. - Optionally bypass internal DSP boot ROM during start-up and execute code directly from Secondary Flash. Use for custom start-up code and In-Application Programming (IAP).
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Up to 40 Multifunction I/O Pins - Increase total DSP system I/O capability - I/O controlled by DSP software or PLD logic
Content Security - Programmable Security Bit blocks access of device programmers and readers
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General purpose PLD - Use for peripheral glue logic to keypads, control panel, displays, LCDs, and other devices - Over 3,000 gates of PLD with 16 macro cells - Eliminate PLDs and external logic devices
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Operating Range - Vcc: 3.3V 10%, Temp: -40oC to +85oC Zero-Power Technology - 50 A standby current typical Flash Memory Speed, Endurance, Retention - 120 ns, 100K cycles, 15 year retention
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February 2002
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TABLE OF CONTENTS Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DSP Address/Data/Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Secondary Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Programmable Logic (PLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Runtime Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 JTAG ISP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Security and NVM Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DSP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ports A, B and C - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Port D - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Port E - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Port F - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Port G - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power On Reset, Warm Reset, Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Programming In-Circuit using JTAG ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC/DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table: CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table: CPLD MicroCell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table: CPLD MicroCell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table: Input MicroCell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table: Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table: Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table: Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table: Reset (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table: ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table: TQFP80 - 80 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table: Pin Assignments - TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table: Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Appendix A. CSIOP REGISTER BIT DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Data-In Registers - Ports A, B, C, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Data-Out Registers - Ports A, B, C, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Direction Registers - Ports A, B, C, D, E, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Drive Registers - Ports A, B, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Drive Registers - Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Enable-Out Registers - Ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Input Macrocells - Ports A, B, C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table: Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table: Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table: PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table: PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table: Memory_ID0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Appendix B. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-21535 BLACKFIN DSP. . . . . . 52 Typical Memory Map, DSM2150F5V and ADSP21535 BLACKFIN DSP . . . . . . . . . . . . . . . . . . . . 53 Specifying the Memory Map with PSDsoft ExpressTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Appendix C. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-21062 SHARC DSP . . . . . . . . 55 Appendix D. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-TS101S TIGERSHARC DSP . 56 Appendix E. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-2191 . . . . . . . . . . . . . . . . . . . . . 57 Appendix F. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-2188M . . . . . . . . . . . . . . . . . . . 58
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SUMMARY DESCRIPTION The DSM2150F5V is an 8 or 16-bit system memory device for use with the Analog Devices DSPs. DSM means Digital signal processor System Memory. A DSM device brings In-System Programmable (ISP) Flash memory, parameter storage, programmable logic, and additional I/O to DSP systems. The result is a flexible two-chip solution for DSP designs. On-chip integrated memory decode logic makes it easy to map dual banks of Flash memory to the DSPs in a variety of ways for bootloading or bypassing DSP boot ROM, code execution, data recording, code swapping, and parameter storage. JTAG ISP reduces development time, simplifies manufacturing flow, and lowers the cost of field upgrades. The JTAG ISP interface eliminates theneed for sockets and pre-programmed memory and logic devices. End products may be manufactured with a blank DSM device soldered down and programmed at the end of the assembly line in 15 to 35 seconds with no involvement of the DSP. Rapidly program test code, then application code as determined by Just-In Time inventory requirements. Additionally, JTAG ISP reduces development time by turning fast iterations of DSP code in the lab. The DSM JTAG interface may be optionally chained with the DSP JTAG debug interface (except ADSP-218x). Code updates in the field require no product disassembly. The FlashLINK TM JTAG programming cable costs $59 USD and plugs into any PC parallel port. Programming through conventional device insertion programmers is also available using PSDpro from STMicroelectronics and other 3rd party programmers. See www.st.com/psd.
DSM devices add programmable logic (PLD) and up to 32 configurable I/O pins to the DSP system. The state of I/O pins can be driven by DSP software or PLD logic. PLD and I/O configuration are programmable by JTAG ISP. The PLD consists of more than 3000 gates and has 16 macro cell registers. Common uses for the PLD include chip-selects for external devices, state-machines, simple shifters and counters, keypad and control panel interfaces, clock dividers, handshake delay, muxes, etc., eliminating the need for small external PLDs and logic devices. Configuration of PLD, I/O, and Flash memory mapping is easily entered in a point-and-click environment using the software development tool, PSDsoft ExpressTM, available at no charge from www.st.com/psd. The two-chip DSP/DSM combination is ideal for systems having limitations on size, EMI levels, and power consumption. DSM memory and logic are "zero-power", meaning they automatically go to standby between memory accesses or logic input changes, producing low active and standby current consumption, which is ideal for battery powered products. A programmable security bit in the DSM protects its contents from unauthorized viewing and copying. When set, the security bit will block access of programming devices (JTAG or others) to the DSM Flash memories and PLD configuration. The only way to defeat the security bit is to erase the entire DSM device, after which the device is blank and may be used again. The DSP will always have access to Flash memory contents through the data bus, even with security bit set.
Figure 2. System Block Diagram, Two Chip Solution
DSM2150F5V DSP SYSTEM MEMORY
I/O FLAGS
SERIAL DEVICE
ANALOG DEVICES DSP ADSP-218x ADSP-219x ADSP-2153x ADSP-2106x ADSP-2116x ADSP-TS101S
ADDR & DECODE LOGIC
ADDRESS
CONTROL
PRIMARY FLASH MEMORY 512K Bytes SECONDARY FLASH MEMORY 32K Bytes
16 I/O PORTS WITH PLD
I/O, PLD, CHIP SELECTS
8 or 16 DATA
I/O BUS
SERIAL DEVICE SDRAM HOST MCU
16 MACROCELL PLD I/O CONTROL POWER MANAGEMENT CONTENT SECURITY
8 to 16 I/O PORTS
GENERAL PURPOSE I/O
JTAG ISP TO ALL AREAS
JTAG ISP
JTAG DEBUG (All But ADSP-218x Family)
AI05732
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Table 1. DSM2150F5V DSP Memory System Devices
Part Number Main Flash Memory 512 KBytes, eight 64KByte sectors Secondary Flash Mem 32 KBytes, four 8 KByte sectors PLD 16 macro cells I/O Ports Up to 40 VCC and I/O Mem Package Op Temp Speed 120 ns 80-pin TQFP -40oC to +85oC
DSM2150F5V-12T6
3.3V 10%
Table 2. Compatible Analog Devices DSPs
DSP Part Number ADSP-2183, 2184L, 2185L, 2186L, 2187L ADSP-2185M, 2186M, 2188M, 2189M ADSP-2184N, 2185N, 2186N, 2187N, 2188N, 2189N ADSP-2191M, 2195M, 2196M Blackfin ADSP-21532S Blackfin ADSP-21535P Sharc ADSP-21060L, 21061L, 21062L, 21065L Sharc ADSP-21160M Sharc ADSP-21160N, 21161N Tiger Sharc ADSP-TS101S Core Operating Voltage 3.3V 2.5V 1.8V 2.5V 3.3V 1.5V 3.3V 2.5V 1.8V 1.0V I/O Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
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Figure 3. TQFP Connections
70 GND
69 VCC 68 PB7
80 PD1
79 PD0
67 PB6
66 PB5
65 PB4
64 PB3
63 PB2
62 PB1
PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND 8 VCC 9 AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20
61 PB0
78 PE7
77 PE6
76 PE5
75 PE4
74 PE3
73 PE2
72 PE1
71 PE0
60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0
PG0 21
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
VCC 29
GND 30
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
RESET 39
CNTL2 40
AI04943
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ARCHITECTURAL OVERVIEW Major functional blocks are shown in Figure 4. DSP Address/Data/Control Interface These DSP signals attach directly to the DSM for a glueless connection. An 8-bit or 16-bit data connection is formed and 16 or more DSP address lines can be decoded as well as various DSP memory strobes; i.e. BMS, RD, AWE, IOMS, MSx, etc. The data path width must be specified as 8bits or 16-bits in PSDsoft Express. This configuraFigure 4. Block Diagram
tion is a static, meaning the data path width cannot switch between 8-bits and 16-bits during runtime. Port F is used for 8-bit data path, Ports F and G are used for 16-bit data path. There are many different ways the DSM2150F5 can be configured and used depending on system requirements. See Appendices for example connections between the DSM2150 and different DSPs.
DSP ADDR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP SECURITY LOCK PAGE REG MAIN FLASH DECODE PLD
8 BLOCKS, 64 KB
I/O PORT TO PLD IN BUS PD0 PD1 PD2 PD3
FS0-7
512 KBytes total SECONDARY FLASH
I/O PORT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
CSBOOT0-3 4 BLOCKS, 8 KB 32 KBytes total CSIOP PLD INPUT BUS RUNTIME CONTROL GPIO PLD POWER MNGMT
DSP DATA PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 DSP DATA or GP I/O PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
I/O PORT PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
ECS0-7 GENERAL PLD AND ARRAY A B AA AA B AAA BBB
BBB
16 OUTPUT MICROCELLS A B A B A B A B A B A B A B A B C C C C CC CC I/O PORT PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
24 INPUT MICROCELLS
PIN FEEDBACK DSP CNTL CNTL0 CNTL1 CNTL2 RST\ NODE FEEDBACK
I/O PORT INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
DSM2150F5V DSP System Memory
JTAG ISP CONTROLLER
Main Flash Memory The 4M bit (512 KByte) Main Flash memory is divided into eight equally-sized 64 KByte sectors that are individually selectable through the Decode PLD. Each Flash memory sector can be located at any address as defined by the user with PSDsoft Express. DSP code and data are easily placed in flash memory using PSDsoft Express, the software development tool.
Secondary Flash Memory The 256 Kbit (32 KByte) Secondary Flash memory is divided into eight equally-sized 8 KByte sectors that are individually selectable through the Decode PLD. Each Flash memory sector can be located at any address as defined by the user with PSDsoft Express. DSP code and data can also be placed Secondary Flash memory using the PSDsoft Express development tool.
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Secondary flash memory is good for storing data because of its smaller sectors. Software EEPROM emulation techniques can be used for small data sets that change frequently on a byte-by-byte basis. Secondary flash may also be used to store custom start-up code for applications that do not "boot" using DMA, but instead start executing code from external memory upon reset (bypass internal DSP boot ROM). Storing code here can keep the entire Main Flash free of initialization code for clean software partitioning. If only one or more 8 KByte sectors are needed for start-up code, the remaining sectors of Secondary Flash may be used for data storage. In-Application-Programming (IAP) may be implemented using Secondary Flash. For example, code to implement IAP over a USB channel may be stored here. The DSP executes code from Secondary Flash array while erasing and writing new code to the Main Flash array as it is received over the USB channel. Any communication channel that the DSP supports can be used for IAP. Secondary Flash may also be used as an extension to Main Flash memory producing a total of 544 KBytes Miscellaneous: Main and Secondary Flash memories are totally independent, allowing concurrent operation. The DSP can read from one memory while erasing or programming the other. The DSP can erase Flash memories by individual sectors or the entire Flash memory array may be erased at one time. Each sector in either Flash memory array may be individually write protected, blocking any writes from the DSP (good for boot and startup code protection). The Flash memories automatically go to standby between DSP read or write accesses to conserve power. Maximum access times include sector decoding time. Maximum erase cycles is 100K and data retention is 15 years minimum. Flash memory, as well as the entire DSM device may be programmed with the JTAG ISP interface with no DSP involvement. Programmable Logic (PLDs) The DSM family contains two PLDS that may optionally run in Turbo or Non-Turbo mode. PLDs operate faster (less propagation delay) while in Turbo mode but consume more power than NonTurbo mode. Non-Turbo mode allows the PLDs to automatically go to standby when no inputs are change to conserve power. The Turbo mode setting is controlled at runtime by DSP software. Decode PLD (DPLD). This is programmable logic used to select one of the eight individual Main Flash memory segments, one of four individual Secondary Flash memory segments, or the group of control registers within the DSM device. The DPLD can also drive external chip select signals on Port C pins. DPLD input signals include: DSP address and control signals, Page Register outputs, DSM Port Pins, CPLD logic feedback. Complex PLD (CPLD). This programmable logic is used to create both combinatorial and sequential general purpose logic. The CPLD contains 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs). PSD Macrocell registers are unique in that that have direct connection to the DSP data bus allowing them to be loaded and read directly by the DSP at runtime. This direct access is good for making small peripheral devices (shifters, counters, state machines, etc.) that are accessed directly by the DSP with little overhead. DPLD inputs include DSP address and control signals, Page Register outputs, DSM Port Pins, and CPLD feedback. OMCs: The general structure of the CPLD is similar in nature to a 22V10 PLD device with the familiar sum-of-products (AND-OR) construct. True and compliment versions of 73 input signals are available to a large AND array. AND array outputs feed into a multiple product-term OR gate within each OMC (up to 10 product-terms for each OMC). Logic output of the OR gate can be passed on as combinatorial logic or combined with a flipflop within in each OMC to realize sequential logic. OMCs can be used as a buried nodes with feedback to the AND array or OMC output can be routed to pins on Port A or Port B. IMCs: Inputs from pins on Ports A, B or C are routed to IMCs for conditioning (clocking or latching) as they enter the chip, which is good for sampling and debouncing inputs. Alternatively, IMCs can pass Port input signals directly to PLD inputs without clocking or latching. The DSP may read the IMCs at any time. Runtime Control Registers A block of 256 bytes is decoded inside the DSM device for control and status registers. 50 registers are used from the block of 256 locations to control the output state of I/O pins, to read I/O pins, to control power management, to read/write macrocells, and other functions at runtime. See Table 4 for description. The base address of these 256 locations is referred to in this data sheet as csiop (Chip Select I/O Port). Individual registers within this block are accessed with an offset from the base address. Some DSPs can access csiop registers using I/O memory with the IOMS strobe (if equipped). csiop registers are bytes. When the DSM is configured for 16-bit operation, csiop registers are read in byte pairs at even addresses only. Care should be taken while writing csiop registers to ensure the proper byte is written within the byte pair. This is not a problem for DSPs that support the BHE (Byte High Enable) signal on the CNTL2 input pin, or
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WRL, WRH (write low byte, write high byte) on the CNTL0 and PD3 input pins of the DSM2150F5V. Memory Page Register This 8-bit register can be loaded and read by the DSP at runtime as one of the csiop registers. Its outputs feed directly into both PLDs. The page register can be used for special memory mapping requirements and also for general logic. I/O Ports The DSM has 52 individually configurable I/O pins distributed over the seven ports (Ports A, B, C, D, E, F, and G). At least 32 I/O are available when DSM2150F5 is connected with 8-bit data path, and at least 24 I/O are available with 16-bit data path. Each I/O pin can be individually configured for different functions such as standard MCU I/O ports or PLD I/O on a pin by pin basis. (MCU I/O means that for each pin, its output state can be controlled or its input value can be read by the DSP at runtime using the csiop registers like an MCU would do.) The static configuration of all Port pins is defined with the PSDsoft ExpressTM software development tool. The dynamic action of the Ports pins is controlled by DSP runtime software. JTAG ISP Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows programming of the entire DSM device or subsections (that is, only Flash memory but not the PLDs) without the participation of the DSP. A blank DSM device soldered to a circuit board can be completely programmed in 15 to 35 seconds. The basic JTAG signals; TMS, TCK, TDI, and TDO form the IEEE-1149.1 interface. The DSM device does not implement the IEEE-1149.1 Boundary Scan functions. The DSM uses the JTAG interface for ISP only. However, the DSM device can reside in a standard JTAG chain with other JTAG devices and it will remain in BYPASS mode while other devices perform Boundary Scan. ISP programming time can be reduced as much as 30% by using two more signals on Port E, TSTAT and TERR in addition to TMS, TCK, TDI and TDO. The FlashLINKTM JTAG programming cable is available from STMicroelectronics for $USD59 and PSDsoft Express software is available at no charge from www.psdst.com. That is all that is needed to program a DSM device using the parallel port on any PC or note-book. See section titled "Programming In-Circuit using JTAG ISP" on page 33. Power Management The DSM has bits in csiop registers that are configured at run-time by the DSP to reduce power consumption of the CPLD. The Turbo bit in the PMMR0 register can be set to logic 1 and the CPLD will go to Non-Turbo mode, meaning it will latch its outputs and go to sleep until the next transition on its inputs. There is a slight penalty in PLD performance (longer propagation delay), but significant power savings are realized. Additionally, other bits in two csiop registers can be set by the DSP to selectively block signals from entering the CPLD which reduces power consumption. Both Flash memories automatically go to standy current between accesses. No user action required. Security and NVM Sector Protection A programmable security bit in the DSM protects its contents from unauthorized viewing and copying. When set, the security bit will block access of programming devices (JTAG or others) to the DSM Flash memory and PLD configuration. The only way to defeat the security bit is to erase the entire DSM device, after which the device is blank and may be used again. Additionally, the contents of each individual Flash memory sector can be write protected (sector protection) by configuration with PSDsoft ExpressTM. This is typically used to protect DSP boot code from being corrupted by inadvertent writes to Flash memory from the DSP. Pin Assignments Pin assignment are shown for the 80-pin TQFPpackage in Figure 3, and their description in Table 3.
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Table 3. Pin Description
Pin Name AD0-15 CNTL0 CNTL1 Type In In In Sixteen address inputs from the DSP. Active low write strobe input from the DSP, typically connected to DSP WR signal. Also functions as WRL for DSPs which use WRL strobe when writing low byte only in 16-bit word. Active low read strobe input from the DSP. Programmable control input. CNTL2 may be used for BHE (Byte High Enable) when DSM2150F5 is configured for 16-bit operation. BHE = 0 will allow a byte write from data lines D8-D15 ignoring data lines D0-D7. BHE = 1 will allow a byte write from D0-D7 ignoring datalines D8-D15. DSP read operatons are not affected by BHE (always read both bytes). Active low reset input from system. Resets DSM I/O Ports, Page Register contents, and other DSM configuration registers. Must be logic Low at Power-up. Eight configurable Port A signals with the following functions: 1. MCU I/O - DSP may write or read pins directly at runtime with csiop registers. 2. CPLD Output Macrocell (McellA0-7) outputs. 3. Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above. Note: PA0-PA7 may be configured at run-time as standard CMOS or Open Drain Outputs. Eight configurable Port B signals with the following functions: 1. MCU I/O - DSP may write or read pins directly at runtime with csiop registers. 2. CPLD Output Macrocell (McellB0-7 or McellC0-7) outputs. 3. Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above. Note: PB0-PB7 may be configured at run-time as standard CMOS or Open Drain Outputs. Eight configurable Port C signals with the following functions: 1. MCU I/O - DSP may write or read pins directly at runtime with csiop registers. 2. DPLD chip-select outputs (ECS0-7, does not consume MicroCells). 3. Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above. Note: PC0-PC7 may be configured at run-time as standard CMOS or Faster Slew Rate Output. Four configurable Port D signals with the following functions: 1. MCU I/O - DSP may write or read pins directly at runtime with csiop registers. 2. Input to the PLDs (no associated Input Macrocells, routes directly into PLDs). Can be used to input address A16 and above. 3. PD1 can be configured as CLKIN, a common clock input to PLD. 4. PD2 can be configured as CSI, active low Chip Select Input to select Flash memory. Flash memory is disabled to conserve more power when CSI is logic high. 5. PD3 can be used for WRH strobe from DSP to write high byte only for 16-bit configuration. Eight configurable Port E signals with the following functions: 1. MCU I/O - DSP may write or read pins directly at runtime with csiop registers. 2. PE0, PE1, PE2, and PE3 can form the JTAG IEEE-1149.1 ISP serial interface as signals TMS, TCK, TDI, and TDO respectively. 3. PE4 and PE5 can form the enhanced JTAG signals TSTAT and TERR respectively. Reduces ISP programming time up to 30% when used in addition to the standard four JTAG signals: TDI, TDO, TMS, TCK. 4. PE4 can be configured as the Ready/Busy output to indicate Flash memory programming status during parallel programming. May be polled by DSP or used as DSP interrupt. Note 1: PE0-PE7 may be configured at run-time as either standard CMOS or Open Drain Outputs. Note 2: The JTAG ISP pins may be multiplexed with other I/O functions. Port F connects to eight data bus signals, D0 - D7 from DSP. Port G connects to eight data bus signals, D8 - D15 from DSP if 16-bit data path is used. Otherwise, PG0-PG7 can be used for general purpose MCU I/O pins. Note: PG0-PG7 may be configured at run-time as standard CMOS or Open Drain Outputs. Supply Voltage Ground pins Description
CNTL2
In
Reset
In
PA0-7
I/O
PB0-7
I/O
PC0-7
I/O
PD0-3
I/O
PE0-7
I/O
PF0-7 PG0-7 VCC GND
I/O I/O
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RUNTIME CONTROL REGISTER DEFINITION A block of 256 addresses are decoded inside the DSM2150F5 for control and status. 50 locations contain registers that the DSP accesses at runtime. The base address of the registers is called csiop (Chip Select I/O Port). Table 4 lists the reg-
isters and their offsets (in hexadecimal) from the csiop base. See Appendix A for bit definitions.
Note: 1. Do not write to unused locations, they should remain logic zero. 2. See Table 13 for register state at reset and at power-on.
Table 4. CSIOP Registers and their Offsets (in hexadecimal)
Register Name Data In Data Out Port Port Port Port Port Port Oth A B C D E G er 00 04 01 05 10 14 11 15 30 34 41 45 Description MCUI/O input mode. Read to obtain current logic level of Port pins. No writes. MCU I/O output mode. Write to set logic level on Port pins. Read to check status. MCU I/O mode. Configures Port pin as input or output. Write to set direction of Port pins. Logic 1 = out, Logic 0 = in. Read to check status. Write to configure Port pins as either standard CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Read to check status. Read to obtain state of IMCs. No writes. Read to obtain the status of the output enable logic on each I/O Port driver. No writes. 20 21 Read to get logic state of output of OMC bank A. Write to load registers of OMC bank A. Read to get logic state of output of OMC bank B. Write to load registers of OMC bank B. Write to set mask for loading OMCs in bank A. Logic 1 in a bit position will block reads/writes of the corresponding OMC. Logic 0 will pass OMC value. Read to check status. Write to set mask for loading OMCs in bank B. Logic 1 in a bit position will block reads/writes of the corresponding OMC. Logic 0 will pass OMC value. Read to check status. Read to determine Main Flash Sector Protection Setting. No writes. Read to determine if DSM devices Security Bit is active. Logic 1 = device secured. Also read to determine Secondary Flash Protection Setting status. No Writes. Write to enable JTAG Pins (optional feature). Read to check status. Power Management Register 0. Write and read. Power Management Register 2. Write and read. Memory Page Register. Write and read. Read to get size of Main Flash memory. No Writes. Read to get size of 2nd Flash memory. No Writes.
Direction
06
07
16
17
36
47
Drive Select Input Macrocells Enable Out Output Macrocells A Output Macrocells B Mask Macrocells A
08 0A 0C
09 0B 0D
18 1A 1C
19
38
49
22
Mask Macrocells B Main Flash Sector Protect Security Bit and Secondary Flash Sector Protection JTAG Enable PMMR0 PMMR2 Page Memory_ID0 Memory_ID1
23
C0
C2
C7 B0 B4 E0 F0 F1
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DETAILED OPERATION Figure 4 shows major functional areas of the device: s Flash Memories
s s s s s
PLDs (DPLD, CPLD, Page Register) DSP Bus Interface (Address, Data, Control) I/O Ports Runtime Control Registers JTAG ISP Interface
The following describes these functions in more detail. Flash Memories The Main Flash memory array is divided into eight equal 64 KByte sectors. The Secondary Flash memory array is divided into four equal 8 KByte sectors. Each sector is selected by the DPLD can be separately protected from program and erase cycles. This configuration is specified by using PSDsoft Express TM. Memory Sector Select Signals. The DPLD generates the Select signals for all the internal memory blocks (see Figure 7). Each of the twelve sectors of the Flash memories has a select signal (FS0-FS7, or CSBOOT0-CSBOOT3) which contains up to three product terms. Having three product terms for each select signal allows a given sector to be mapped into multiple areas of system memory if needed. Ready/Busy (PE4). This signal can be used to output the Ready/Busy status of the device. Ready/ Busy is a 0 (Busy) when either Flash memory array is being written, or when either Flash memory array is being erased. The output is a 1 (Ready) when no Write or Erase cycle is in progress. This signal may be polled by the DSP or used as a DSP interrupt to indicate when an erase or program cycle is complete.
Memory Operation. The Flash memories are accessed through the DSP Address, Data, and Control Bus Interface. DSPs and MCUs cannot write to Flash memory as it would an SRAM device. Flash memory must first be "unlocked" with a special sequence of write operations to invoke an internal algorithm, then a single data byte (or word if DSM2150F5 is configured for 16-bit operation) is written to the Flash memory array, then programming status is checked by a read operation or by checking the Ready/Busy pin (PE4). This "unlocking" sequence optionally may be bypassed by using the Unlock Bypass command to reduce programming time . Table 5 lists all of the special instruction sequences to program (write) data to the Flash memory arrays, erase the arrays, and check for different types of status from the arrays when the DSM2150F5 is configured to operate as an 8-bit device. Table 6 lists instruction sequences when the DSM2150 is configured for 16-bit operation. These instruction sequences are different combinations of individual write and read operations. IMPORTANT: The DSP cannot read and execute code from the same Flash memory array for which it is directing an instruction sequence. Or more simply stated, the DSP may not read code from the same Flash array that is writing or erasing. Instead, the DSP must execute code from an alternate memory (like its own internal SRAM or a different Flash array) while sending instructions to a given Flash array. Since the two Flash memory arrays inside the DSM device are completely independent, the DSP may read code from one array while sending instructions to the other. After a Flash memory array is programmed (written) it will go to "Read Array" mode, then the DSP can read from Flash memory just as if would from any ROM or SRAM device.
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Table 5. Instruction Sequences for 8-bit Operaton1,2,3,4
Instruction Sequence
Read Memory Contents5 Read Flash Identifier (Main Flash only)6,7 Read Memory Sector Protection Status6,7,8 Program a Flash Byte Flash Bulk Erase9
Cycle 1
Read byte from any valid Flash memory addr Write AAh to XX555h Write AAh to XX555h Write AAh to XX555h Write AAh to XX555h Write AAh to XX555h Write B0h to addr in FS0-7 or CSBOOT0-3 Write 30h to addr in FS0-7 or CSBOOT0-3 Write F0h to addr in FS0-7 or CSBOOT0-3 Write AAh to XX555h Write A0h to addr in FS0-7 or CSBOOT0-3 Write 90h to addr in FS0-7 or CSBOOT0-3
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Write 55h to XXAAAh Write 55h to XXAAAh Write 55h to XXAAAh Write 55h to XXAAAh Write 55h to XXAAAh
Write 90h to XX555h Write 90h to XX555h Write A0h to XX555h Write 80h to XX555h Write 80h to XX555h
Read identifier at addr XXX01h Read value at addr XXX02h Write (program) data to addr Write AAh to XX555h Write AAh to XX555h Write 55h to XXAAAh Write 55h to XXAAAh Write 10h to XX555h Write 30h to another Sector Write 30h to another Sector
Flash Sector Erase10
Suspend Sector Erase11 Resume Sector Erase12 Reset Flash6
Unlock Bypass Unlock Bypass Program13 Unlock Bypass Reset14
Write 55h to XXAAAh Write (program) data to addr Write 00h to addr in FS0-7 or CSBOOT0-3
Write 20h to XX555h
Note: 1. All values are in hexadecimal, X = Don't Care 2. A desired internal Flash memory sector select signal (FS0 - FS7 or CSBOOT0 - CSBOOT3) must be active for each write or read cycle. Only one of these sector select signals will be active at any given time depending on the address presented by the DSP and the memory mapping defined in PSDsoft Express. FS0 - FS7 and CSBOOT0-CSBOOT3 are active high logic internally. 3. Only address bits A11-A0 are used during Flash memory instruction sequence decoding bus cycles. The individual sector select signal (FS0 - FS7 or CSBOOT0-CSBOOT3) which is active during the instruction sequences determines the complete address. 4. For write operations, addresses are latched on the falling edge of Write Strobe (WR, CNTL0), Data is latched on the rising edge of Write Strobe (WR, CNTL0) 5. No Unlock or Instruction cycles are required when the device is in the Read Array mode. Operation is like reading a ROM device. 6. The Reset Flash instruction is required to return to the normal Read Array mode if the Error Flag (DQ5) bit goes High, or after reading the Flash Identifier or after reading the Sector Protection Status. 7. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruction sequence is intended. The DSP must fetch, for example, the code from the DSP SRAM when reading the Flash memory Identifier or Sector Protection Status. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 9. Directing this command to any individual active Flash memory segment (FS0 - FS7) will invoke the bulk erase of all eight Flash memory sectors. Likewise, directing command to any Secondary Flash sector (CSBOOT0-3) will invoke erase of all four sectors. 10. DSP writes command sequence to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. 30h must be addressed to one of the other Flash memory segments (FS0-7 or CSBOOT0-3) for each additional segment (write 30h to any address within a desired sector). No more time than tTIMEOUT can elapse between subsequent additional sector erase commands. 11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protect Status, when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction sequence is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction sequence is valid only during the Suspend Sector Erase mode. 13. The Unlock Bypass instructionis required prior to the Unlock Bypass Program Instruction. 14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in Umlock Bypass mode.
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Table 6. Instruction Sequences for 16-bit Operaton1,2,3,4,15
Instruction Sequence
Read Memory Contents5 Read Flash Identifier (Main Flash only)6,7 Read Sector ProtectStatus6,7,8 Program a Flash word Flash Bulk Erase9 Flash Sector Erase10 Suspend Sector Erase11 Resume Sector Erase12 Reset Flash6
Cycle 1
Read word from even addr Write XXAAh to XXAAAh Write XXAAh to XXAAAh Write XXAAh to XXAAAh Write XXAAh to XXAAAh Write XXAAh to XXAAAh Write XXB0h to even addr in FS07 or CSBOOT0-3 Write XX30h to even addr in FS07 or CSBOOT0-3 Write XXF0h to even addr in FS07 or CSBOOT0-3 Write XXAAh to XXAAAh Write XXA0h to even addr in FS07 or CSBOOT0-3 Write XX90h to even addr in FS07 or CSBOOT0-3
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Write XX55h to XX554h Write XX55h to XX554h Write XX55h to XX554h Write XX55h to XX554h Write XX55h to XX554h
Write XX90h to XXAAAh Write XX90h to XXAAAh Write XXA0h to XXAAAh Write XX80h to XXAAAh Write XX80h to XXAAAh
Read identifier at addr XXX02h Read value at addr XXX04h Write word to even address Write XXAAh to XXAAAh Write XXAAh to XXAAAh Write XX55h to XX554h Write XX55h to XX554h Write XX10h to XXAAAh Write XX30h to new Sectr Write XX30h to new Sector
Unlock Bypass Unlock Bypass Program13 Unlock Bypass Reset14
Write XX55h to XX554h Write word to even addr Write XX00h to even addr in FS07 or CSBOOT0-3
Write XX20h to XXAAAh
Note: 1. All values are in hexadecimal, X = Don't Care 2. A desired internal Flash memory sector select signal (FS0 - FS7 or CSBOOT0 - CSBOOT3) must be active for each write or read cycle. Only one of these sector select signals will be active at any given time depending on the address presented by the DSP and the memory mapping defined in PSDsoft Express. FS0 - FS7 and CSBOOT0-CSBOOT3 are active high logic internally. 3. Only address bits A11-A0 are used during Flash memory instruction sequence decoding bus cycles. The individual sector select signal (FS0 - FS7 or CSBOOT0-CSBOOT3) which is active during the instruction sequences determines the complete address. 4. For write operations, addresses are latched on the falling edge of Write Strobe (WR, CNTL0), Data is latched on the rising edge of Write Strobe (WR, CNTL0) 5. No Unlock or Instruction cycles are required when the device is in the Read Array mode. Operation is like reading a ROM device. 6. The Reset Flash instruction is required to return to the normal Read Array mode if the Error Flag (DQ5) bit goes High, or after reading the Flash Identifier or after reading the Sector Protection Status. 7. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruction sequence is intended. The DSP must fetch, for example, the code from the DSP SRAM when reading the Flash memory Identifier or Sector Protection Status. 8. The data is XX00h for an unprotected sector, and XX01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 9. Directing this command to any individual active Flash memory segment (FS0 - FS7) will invoke the bulk erase of all eight Flash memory sectors. Likewise, directing command to any Secondary Flash sector (CSBOOT0-3) will invoke erase of all four sectors. 10. DSP writes command sequence to initial segment to be erased, then writes the word XX30h to additional sectors to be erased. XX30h must be addressed to one of the other Flash memory segments (FS0-7 or CSBOOT0-3) for each additional segment (write XX30h to any address within a desired sector). No more time than tTIMEOUT can elapse between subsequent additional sector erase commands. 11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protect Status, when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction sequence is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction sequence is valid only during the Suspend Sector Erase mode. 13. The Unlock Bypass instructionis required prior to the Unlock Bypass Program Instruction. 14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in Umlock Bypass mode. 15. All bus cycles in an instruction sequence are writes or reads to an even address (XXAAAh or XX554h), and only the low byte, D0D7, is significant (upper byte on D8-D15 is ignored). A Flash memory Program bus cycle writes a word to an even address.
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Instruction Sequences An instruction sequence consists of a sequence of specific write or read operations. IMPORTANT: When the DSM2150F5 is configured for 8-bit operations, all instruction sequences consist of byte write and read operations on an even or odd address boundary. Flash memory locations are programmed in bytes to even or odd addresses. When the DSM2150F5 is configured for 16-bit operation, all instruction sequences consist of word write and read operations on even address boundaries only. The lower byte on D0-7 is significant and the upper byte on D8-15 is ignored during instructions and status. Flash memory locations are programmed in 16-bit words to even addresses only. Each byte/word written to the device is received and sequentially decoded and not executed as a standard write operation to the memory array until the entire command string has been received. The instruction sequence is executed when the correct number of bytes/words are properly received and the time between two consecutive bytes/words is shorter than the time-out period, tTIMEOUT. Some instruction sequences are structured to include read operations after the initial write operations. The instruction sequence must be followed exactly. Any invalid combination of instruction bytes/ words or time-out between two consecutive bytes/ words while addressing Flash memory resets the device logic into Read Array mode (Flash memory is read like a ROM device). The device supports the instruction sequences summarized in Table 5 and Table 6: Flash memory: s Read memory contents
s s s s s s s
Read Main Flash Identifier value Read Sector Protection Status Program a Byte/Word Erase memory by chip or sector Suspend or resume sector erase Reset to Read Array mode Unlock Bypass Instructions
For efficient decoding of the instruction sequences, the first two bytes/words of an instruction sequence are the coded cycles and are followed by an instruction byte/word or confirmation byte/ word. The coded cycles consist of writing the data AAh to address XX555h (or XXAAh to address
XXAAAh for 16-bit mode) during the first cycle and data 55h to address XXAAAh (or XX55h to address XX554 for 16-bit mode) during the second cycle. Address inpur signals A12 and above are Don't Care during the instruction sequence Write cycles. However, the appropriate internal Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected internally (active is logic 1). Reading Flash Memory Under typical conditions, the DSP may read the Flash memory using read operations just as it would a ROM or RAM device. Alternately, the DSP may use read operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the DSP may use instruction sequences to read special data from these memory blocks. The following sections describe these read instruction sequences. Read Memory Contents. Flash memory is placed in the Read Array mode after Power-up, chip reset, or a Reset Flash memory instruction sequence (see Table 5 or 6). The DSP can read the memory contents of the Flash memory by using read operations any time the read operation is not part of an instruction sequence. Bytes are read from even or odd addresses when the DSM2150F5 is configured for 8-bit operation. Only 16-bit words are read from even addresses when the DSM2150F5 is configured for 16-bit operations. Read Main Flash Identifier. The Main Flash memory identifier is read with an instruction sequence composed of 4 operations: 3 specific write operations and a read operation (see Table 5 or 6). During the read operation the appropriate internal Sector Select (FS0-FS7) must be active. The identifier is E8h (or XXE8h for 16-bit mode). Not applicable to Secondary Flash. Read Memory Sector Protection Status. The Flash memory Sector Protection Status is read with an instruction sequence composed of 4 operations: 3 specific write operations and a read operation (see Table 5 or 6). The read operation will produce 01h (XX01h for 16-bit mode) if the Flash sector is protected or 00h (XX00h or 16-bit mode) if the sector is not protected. Internal Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. Alternatively, the sector protection status can also be read by the DSP accessing the Flash memory Protection registers in csiop space. See the section entitled "Flash Memory Sector Protect" for register definitions.
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Table 7. Status Bit Definition
Functional Block FS0-FS7, or CSBOOT0-CSBOOT3 Active (the desired segment is selected) DQ7 Data Polling DQ6 Toggle Flag DQ5 Error Flag DQ4 DQ3 Erase Timeout DQ2 DQ1 DQ0
Flash Memory
X
X
X
X
Note: 1. X = Not guaranteed value, can be read either 1 or 0. 2. DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. When the DSM2150F5 is configured for 16-bit operation, DQ8-DQ15 are not significant and can be ignored.
Reading the Erase/Program Status Bits. The device provides several status bits to be used by the DSP to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the DSP spends performing these tasks and are defined in Table 7. The status bits can be read as many times as needed. DQ8 DQ15 are insignificant and can be ignored when the DSM2150F5 is configured to operate in 16-bit mode, however, the read operation must occur on an even address boundary. For Flash memory, the DSP can perform a read operation to obtain these status bits while an Erase or Program instruction sequence is being executed by the embedded algorithm. See the section entitled "Programming Flash Memory", on page 18, for details. Data Polling Flag (DQ7). When erasing or programming in Flash memory, the Data Polling Flag (DQ7) bit outputs the complement of the bit being entered for programming/writing on the Data Polling Flag (DQ7) bit. Once the Program instruction sequence or the write operation is completed, the true logic value is read on the Data Polling Flag (DQ7) bit. s Data Polling is effective after the fourth Write pulse (for a Program instruction sequence) or after the sixth Write pulse (for an Erase instruction sequence). It must be performed at the address being programmed or at an address within the Flash memory sector being erased.
s
Toggle Flag (DQ6). The device offers an alternative way for determining when the Flash memory Program cycle is completed. During the internal write operation and when the Sector Select FS0FS7 (or CSBOOT0-CSBOOT3) is true, the Toggle Flag (DQ6) bit toggles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory. When the DSM2150F5 is configured to operate in 16-bit mode, status reads must occur at even addresses, DQ8 - DQ15 are insignificant and can be ignored. When the internal cycle is complete, the toggling stops and the data read on the Data Bus is the addressed memory byte/word. The device is now accessible for a new read or write operation. The cycle is finished when two successive reads yield the same output data. s The Toggle Flag (DQ6) bit is effective after the fourth write operation (for a Program instruction sequence) or after the sixth write operation (for an Erase instruction sequence).
s
If the byte/word to be programmed belongs to a protected Flash memory sector, the instruction sequence is ignored. If all the Flash memory sectors selected for erasure are protected, the Toggle Flag (DQ6) bit toggles to 0 for tTIMOUT and then returns to the previous addressed byte.
s
During an Erase cycle, the Data Polling Flag (DQ7) bit outputs a 0. After completion of the cycle, the Data Polling Flag (DQ7) bit outputs the last bit programmed (it is a 1 after erasing). If the byte/word to be programmed is in a protected Flash memory sector, the instruction sequence is ignored. If all the Flash memory sectors to be erased are protected, the Data Polling Flag (DQ7) bit is reset to 0 for tTIMOUT, and then returns to the previous addressed byte. No erasure is performed.
s
s
Error Flag (DQ5). During a normal Program or Erase cycle, the Error Flag (DQ5) bit is to 0. This bit is set to 1 when there is a failure during Flash memory byte/word Program operation, Sector Erase, or Bulk Erase operation. In the case of Flash memory programming, the Error Flag (DQ5) bit indicates the attempt to program a Flash memory bit from the programmed state, logic 0, to the erased state, logic 1, which is not valid. The Error Flag (DQ5) bit may also indicate a Time-out condition while attempting to program a byte/word. In case of an error in a Flash memory Sector Erase or byte/word Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte/word belongs must no longer be used. Other Flash memory sectors may still be
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used. The Error Flag (DQ5) bit is reset after a Reset Flash instruction sequence. Erase Time-out Flag (DQ3). The Erase Timeout Flag (DQ3) bit reflects the time-out period allowed between two consecutive Sector Erase instruction sequence bytes/words. The Erase Timeout Flag (DQ3) bit is reset to 0 after a Sector Erase cycle for a time period tTIMOUT unless an additional Sector Erase instruction sequence is decoded. After this time period, or when the additional Sector Erase instruction sequence is decoded, the Erase Time-out Flag (DQ3) bit is set to 1. Programming Flash Memory When the DSM2150F5 is configured for 8-bit operation, Flash memory locations are programmed in 8-bit bytes to even or odd addresses. When the DSM2150F5 is configured for 16-bit operation, Flash memory locations are programmed in 16-bit words to even addresses only. However, some DSPs support the BHE (byte high enable) signal on the DSM2150F5V CNTL2 input or the WRL, WRH (write low byte, write high byte) signals on the CNTL0 and PD3 inputs. In these cases, a DSP write operation can be directed to an individual byte (upper or lower) of a byte-pair. These signals do not effect read operations, only writes. Reads are always by 16-bits from an even address. BHE signal on CNT2 input. See Table 8. Evenbyte refers to locations with address A0 equal to 0, and odd byte as locations with A0 equal to 1. Table 8. 16-Bit Data Bus with BHE
BHE 0 0 1 A0 0 1 0 D15-D8 Odd Byte Odd Byte -- D7-D0 Even Byte -- Even Byte
WRL and WRH signals on CNT0 and PD3 inputs. See Table 9. Even-byte refers to locations with address A0 equal to 0, and odd byte as locations with A0 equal to 1. Table 9. 16-Bit Data Bus with WRH and WRL
WRH 0 0 1 WRL 0 1 0 D15-D8 Odd Byte Odd Byte -- D7-D0 Even Byte -- Even Byte
When a byte/word of Flash memory is programmed, individual bits are programmed to logic 0. You cannot program a bit in Flash memory to a
logic 1 once it has been programmed to a logic 0. A bit must be erased to logic 1, and programmed to logic 0. That means Flash memory must be erased prior to being programmed. The DSP may erase the entire Flash memory array all at once or individual sector-by-sector, but not byte-by-byte (or word-by-word for 16-bit mode). However, the DSP may program Flash memory byte-by-byte (or word-by-word for 16-bit mode). The Flash memory requires the DSP to send an instruction sequence to program a byte or to erase sectors (see Table 5 or 6). Once the DSP issues a Flash memory Program or Erase instruction sequence, it must check for the status bits for completion. The embedded algorithms that are invoked inside the device provide several ways give status to the DSP. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (pin PE4). Data Polling. Polling on the Data Polling Flag (DQ7) bit is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 5 shows the Data Polling algorithm. When the DSP issues a Program instruction sequence, the embedded algorithm within the device begins. The DSP then reads the location of the byte/word to be programmed in Flash memory to check status. For 16-bit operation, the status location read must be at an even address and D8-D15 can be ignored. The Data Polling Flag (DQ7) bit of this location becomes the compliment of bit 7 of the original data byte/word to be programmed. The DSP continues to poll this location, comparing the Data Polling Flag (DQ7) bit and monitoring the Error Flag (DQ5) bit. When the Data Polling Flag (DQ7) bit matches bit7 of the original data, and the Error Flag (DQ5) bit remains 0, then the embedded algorithm is complete. If the Error Flag (DQ5) bit is 1, the DSP should test the Data Polling Flag (DQ7) bit again since the Data Polling Flag (DQ7) bit may have changed simultaneously with the Error Flag (DQ5) bit (see Figure 5). The Error Flag (DQ5) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte/word or if the DSP attempted to program a 1 to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte/word hat was written to the Flash memory with the byte/word that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 5 still applies. However, the Data Polling Flag (DQ7) bit is 0 until the Erase cycle is complete. A 1 on the Error Flag (DQ5) bit indicates a time-out condition on the Erase cycle, a
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0 indicates no error. The DSP can read any location (must be even address for 16-bit mode) within the sector being erased to get the Data Polling Flag (DQ7) bit and the Error Flag (DQ5) bit. PSDsoft Express generates ANSI C code functions which implement these Data Polling algorithms. Figure 5. Data Polling Flowchart
START
logic functions can be constructed using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. Table 10. DPLD and CPLD Inputs
Input Source DSP Address Bus1 DSP Control Signals2 Reset Input Name A15-A0 CNTL2-CNTL0 RST Number of Signals 16 3 1 8 8 8 4 8 8 8 1
READ DQ5 & DQ7 at VALID ADDRESS
PortA Input Macrocells PA7-PA0 PortB Input Macrocells PB7-PB0 PC7-PC0 PD3-PD0 PG7-PG0 MCELLA FB7-0 MCELLB FB7-0 Ready/Busy
DQ7 = DATA NO
YES
PortC Input Macrocells Port D Inputs Page Register
NO
DQ5 =1 YES READ DQ7
Macrocell A Feedback Macrocell B Feedback Flash memory Program Status Bit
DQ7 = DATA NO FAIL
YES
Note: 1. DSP address lines above A15 may enter the DSM device on any pin on ports A, B, C or D. See Appendices for recommended connections. 2. Additional DSP control signals may enter the DMS device on any pin on Ports A, B, C, or D. See Appendices for recommended connections.
PASS
AI01369B
PLDs The PLDs bring programmable logic to the device. After specifying the logic for the PLDs using PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PLDs have selectable levels of performance and power consumption. The device contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD), as shown in Figure 6. The DPLD performs address decoding, and generates select signals for internal and external components, such as memory, registers, and I/O ports. The DPLD can generate eight External Chip Select (ECS0-ECS7) signals on Port C. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These
The AND Array is used to form product terms. These product terms are configured from the logic definition entered in PSDsoft Express. A PLD Input Bus consisting of 73 signals is connected to the PLDs. Input signals are shown in Table 10. Turbo Bit. The PLDs in the device can minimize power consumption by switching to standby when inputs remain unchanged for an extended time tTURBO. Resetting the Turbo bit to 0 (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. Additionally, seven bits are available in the PMMR registers in csiop to block DSP control signals from entering the PLDs. This reduces power consumption and can be used only when these DSP control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections.
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Figure 6. PLD Diagram
8
PAGE REGISTER
Data Bus
73
DECODE PLD (DPLD)
8 4
Main Flash Memory Selects Secondary Flash Memory Selects
1 8 1
CSIOP Select External Chip Selects to Port C JTAG Select
PLD INPUT BUS
16
Output Macrocell Feedback
Direct Macrocell Access from MCU Data Bus
CPLD
PT ALLOC.
16 Output Macrocell
MCELLA to PORT A
8
I/O PORTS
73
24 Input Macrocell (PORT A, B,C)
MCELLB to PORT B
8
Direct Macrocell Input to MCU Data Bus 24 Input Macrocell and Input Ports
4
PORT D Inputs
AI05769
Decode PLD (DPLD) The DPLD, shown in Figure 7, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: s 8 Main Flash memory Sector Select (FS0-FS7) signals with three product terms each
s
s
1 internal csiop select for DSM device control and status registers (csiop is the base address of the block of 256 byte locations) 1 JTAG Select signal (enables JTAG operations on Port E when multiplexing JTAG signals with general I/O signals) 8 external chip select output signals for Port C pins, each with one product term.
s
4 Secondary Flash memory Sector Select (CSBOOT0-CSBOOT3) signals with three product terms each
s
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Figure 7. DPLD Logic Array
3 3 3 3 (INPUTS) I/O PORTS (PORT A, B,C) MCELLA.FB [ 7:0] (Feedback) MCELLB.FB [ 7:0] (Feedback ) PG0-PG7 A[15:0] PD[3:0] (24) 3 (8) 3 (8) 3 (8) 3 (16) 3 (4) 3 CNTRL[2:0] (Read/Write Control Signals)(3) 3 RESET RD_BSY (1) (1) 1 1 1 1 1 CSIOP JTAGSEL ECS0 ECS1 ECS2 I/O Decoder Select JTAG ISP 3 CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 Flash Main Memory Sector Selects 4 Secondary Flash Memory Sector Selects
1 1 1 1 1
ECS3 ECS4 ECS5 ECS6 ECS7
External Chip Selects to PORT C
AI05775
Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. See application note AN1171 for details on how to specify logic using PSDsoft Express. The CPLD has the following blocks: s 24 Input Macrocells (IMC)
s s
s
AND Array capable of generating up to 190 product terms Two I/O Ports.
s
16 Output Macrocells (OMC) Product Term Allocator
Each of the blocks are described in the sections that follow. The IMCs and OMCs are connected to the device internal data bus and can be directly accessed by the DSP. This enables the DSP software to load data into the OMC or read data from both the IMCs and OMCs. This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macro cell architectures.
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Figure 8. Macrocell and I/O Port
PLD INPUT BUS Product Terms from other MacrocellS DSP ADDRESS / DATA BUS
CPLD Macrocells
PT PRESET PRODUCT TERM ALLOCATOR MCU DATA IN MCU LOAD DATA LOAD CONTROL
I/O PORTS
DATA WR
I/O Pin
D Q MUX
AND ARRAY
UP TO 10 PRODUCT TERMS Macrocell Out to MCU CPLD OUTPUT
PR DI LD PT CLOCK D/T MUX Q COMB. /REG SELECT PDR INPUT
PLD INPUT BUS
GLOBAL CLOCK CLOCK SELECT PT CLEAR
D/T/JK FF SELECT CK CL
MUX
POLARITY SELECT
D WR
Q DIR REG.
PT Output Enable (OE) Macrocell Feedback I/O Port Input
Input Macrocells
MUX QD
QD PT INPUT LATCH GATE/CLOCK G
AI05770
Output Macrocell (OMC). Eight of the OMCs, McellA0-McellA7, are connected to Port A pins. The other eight Macrocells, McellB0-McellB7, are connected to Ports B pins. OMCs may be used for internal feedback (buried registers), or their outputs may be routed to external Port pins. The OMC architecture is shown in Figure 9. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other OMC. The polarity of the product term is controlled by the XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or com-
binatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the OMC block can be configured as a D, T, JK, or SR type in PSDsoft ExpressTM. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms.
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Table 11. Output Macrocell Port and Data Bit Assignments
Output Macrocell McellA0 McellA1 McellA2 McellA3 McellA4 McellA5 McellA6 McellA7 McellB0 McellB1 McellB2 McellB3 McellB4 McellB5 McellB6 McellB7 Port Assignment Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Native Product Terms 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Maximum Borrowed Product Terms 6 6 6 6 6 6 6 6 5 5 5 5 6 6 6 6 Data Bit for Loading or Reading in 16-bit Mode D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Data Bit for Loading or Reading in 8-bit Mode D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Product Term Allocator. The CPLD has a Product Term Allocator. PSDsoft ExpressTM uses the Product Term Allocator to borrow and place product terms from one Macrocell to another. This happens automatically in PSDsoft ExpressTM, but understanding how allocation works will help you if your logic design does not "fit", in which case you may try selecting a different pin or different OMC where the allocation resources may differ and the design will then fit. The following list summarizes how product terms are allocated: s McellA0-McellA7 all have three native product terms and may borrow up to six more
s
McellB0-McellB3 all have four native product terms and may borrow up to five more McellB4-McellB7 all have four native product terms and may borrow up to six more.
s
Each Macrocell may only borrow product terms from certain other Macrocells. Product terms already in use by one Macrocell are not available for another Macrocell. Product term allocation does not add any propagation delay to the logic. If an equation requires more product terms than are available to it through product term allocation,
then "external" product terms are required, which consumes other OMC. This is called product term expansion and also happens automatically in PSDsoft Express TM as needed. Product tern expansion causes additional propagation delay because an OMC is consumed by the expansion and it's output is rerouted (or fed back) into the AND array. You can examine the fitter report generated by PSDsoft Express to see resulting product term allocation and product term expansion. Loading and Reading the OMCs. Each of the two OMC blocks (8 OMCs each) occupies a memory location in the DSP address space, as defined in the csiop block MCELLA0-7 and MCELLB0-7 (see Table 4). The flip-flops in each of the 16 OMCs can be loaded from the data bus by a DSP. Loading the OMCs with data from the DSP takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the DSP. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data is loaded into the OMC on the trailing edge of Write Strobe coming from CNTL0.
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Figure 9. CPLD Output Macrocell
MASK REG.
Output Macrocell CS RD
INTERNAL DATA BUS
PT Allocator
WR Direction Register ENABLE (.OE) PRESET(.PR) COMB/REG SELECT
AND ARRAY
PT PT DIN PR
PLD INPUT BUS
MUX PT LD POLARITY SELECT CLEAR (.RE) PT CLK CLKIN MUX IN CLR Programmable FF (D / T/JK /SR) Port Driver Q
I/O Pin
Feedback (.FB) Port Input Input Macrocell
AI05771
The OMC Mask Register. There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers can be used to block the loading of data to individual OMCs. The default value for the Mask Registers is 00h, which allows loading of all the OMCs. When a given bit in a Mask Register is set to a 1, the DSP is blocked from writing to the associated OMC. For example, suppose McellA0-3 are being used for a state machine. You would not want a DSP write to McellA to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellA group with the value 0Fh.
The Output Enable of the OMC. The OMC block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. If the OMC output is specified as an internal node and not as a port pin output in the PSDsoft Express, then the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array.
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Figure 10. Input Macrocell
INTERNAL DATA BUS
INPUT MACROCELL _ RD ENABLE ( .OE ) OUTPUT Macrocells BC AND Macrocells AB
DIRECTION REGISTER
PT AND ARRAY
I/O Pin PT
PLD INPUT BUS
Port Driver
MUX
Q
D PT
D FF Feedback Q D G LATCH Input Macrocell
AI04904C
Input Macrocells (IMC). The CPLD has 24 IMCs, one for each pin on Ports A, B and C. The architecture of the IMCs is shown in Figure 10. The IMCs are individually configurable, and can be used as a latch, a register, or to pass incoming Port signals prior to driving them onto the PLD input bus. This is useful for sampling and debouncing inputs to the AND array (keypad inputs, etc.). Additionally, the outputs of the IMCs can be read by the DSP asynchronously at any time through the internal data bus using the csiop register block (see Table 4). The enable for the latch and clock for the register are driven by a product term from the CPLD. Each product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the IMCs are specified by equations specified in PSDsoft Express. See Application note AN1171. DSP Bus Interface The "no-glue logic" DSP Bus Interface allows direct connection. DSP address, data, and control signals connect directly to the DSM device. See Appendices for typical connections.
DSP address, data and control signals are routed to Flash memory, I/O control (csiop), OMCs, and IMCs within the DMS. The DSP address range for each of these components is specified in PSDsoft Express TM. I/O Ports There are seven programmable I/O ports: Ports A, B, C, D, E, F, and G. However, typically only four of these ports are available in 8-bit DSP data configuration, and 3 ports with 16-bit data. Each of the ports is eight bits except Port D, which is 4 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft ExpressTM or by the DSP writing to on-chip registers in the csiop block. The topics discussed in this section are: s General Port architecture
s s s s
Port operating modes
csiop Port registers
Port Data Registers Individual Port functionality.
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Figure 11. General Port Architecture
DATA OUT REG. D WR PORT PIN OUTPUT MUX Macrocell Outputs EXT CS INTERNAL DATA BUS READ MUX P D B DATA IN Q
DATA OUT
ENABLE OUT
DIR REG. D WR ENABLE PRODUCT TERM (.OE) Input Macrocell CPLD - INPUT
AI05772
Q
General Port Architecture. The general architecture of the I/O Port block is shown in Figure 12. Individual Port architectures are shown in Figure n to Figure 14. In general, once the purpose for a port pin has been defined in PSDsoft ExpressTM, that pin is no longer available for other purposes. Exceptions are noted. The ports contain an output multiplexer whose select signals are driven by the configuration bits determined by PSDsoft Express. Inputs to the multiplexer include the following: s Output data from the Data Out register (for MCU I/O mode)
s s
CPLD Macrocell output (OMC) External Chip Selects ESC0-7 from the DPLD to Port C pins only.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read by the DSP. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the DSP. The Data Out and Macrocell outputs, Direction and Drive Registers, and port pin
input are all connected to the Port Data Buffer (PDB). The Port pin's tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in PSDsoft Express TM, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the DSP. The Port Data Buffer (PDB) feedback path allows the DSP to check the contents of the registers. Ports A, B, and C have IMCs. The IMCs can be configured as registers (for sampling or debouncing), as transparent latches, or direct inputs to the PLDs. The registers and latches are clocked by a product term from the PLD AND Array. The outputs from the IMCs drive the PLD input bus and can be read by the DSP. See the section entitled "Input Macrocell", on page 25.
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Table 12. Port Operating Modes
Port Mode MCU I/O DSP data bus for 8-bit config DSP data bus for 16-bit config PLD Input though IMC PLD Input directly McellA Outputs McellB Outputs Additional External CS Outputs JTAG ISP Port A Yes No No Yes No Yes No No No Port B Yes No No Yes No No Yes No No Port C Yes No No Yes No No No Yes No Port D Yes No No No Yes No No No No Port E Yes No No No No No No No Yes1 Port F No Yes Yes No No No No No No Port G Yes2 No Yes No No No No No No
Note: 1. Can be multiplexed with other I/O functions. 2. Only in 8-bit DSP data bus configuation.
Port Operating Modes The I/O Ports have several modes of operation. Modes are defined using PSDsoft ExpressTM, and then runtime control from the DSP can occur using the registers in the csiop block. See Application Note AN1171 for more detail. Table 12 summarizes which modes are available on each port. Each of the port operating modes are described in the following sections. MCU I/O Mode. In MCU I/O mode, DSP I/O Ports are expanded. The DSP can read I/O pins, set the direction of I/O pins, and change the state of I/O pins by accessing the registers in the csiop block. The csiop registers (Data In, Data Out, and Direction) that implement MCU I/O mode are defined Table 4 and Appendix A. Data In Register for MCU I/O mode. The DSP may read the Data In registers in the csiop block at any time to determine the logic state of a Port pin. This will be the state at the pin regardless of whether it is driven by a source external to the DSM or driven internally from the DSM device. Reading a logic zero for a bit in a Data In register means the corresponding Port pin is also at logic zero. Reading logic one means the pin is logic one. Each bit in a Data In register corresponds to an individual Port pin. For a given Port, bit 0 in a Data In register corresponds to pin 0 of the Port. Example, bit 0 of the Data In register for Port B corresponds to Port B pin PB0. Data Out Register for MCU I/O Mode. The DSP may write (or read) the Data Out register in the csiop block at any time. Writing the Data Out register will change the logic state of a Port pin only if it is not driven or controlled by the CPLD. Writing a logic zero to a bit in a Data Out register will force the corresponding Port pin to be logic zero. Writing logic one will drive the pin to logic one. Each bit in the Data Out registers correspond to Port pins the same way as the Data In registers described above. When some pins of a Port are driven by the CPLD, writing to the corresponding bit in a Data
Out register will have no effect as the CPLD overrides the Data Out register. Direction Register for MCU I/O mode. The Direction Register, in conjunction with the output enable, controls the direction of data flow in the I/O Ports. Any bit set to 1 in the Direction Register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. The default mode for all port pins is input. Figure n shows the Port Architecture for Ports A, B and C. The direction of data flow for are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction Register has sole control of a given pin's direction. Drive Select Register. The Drive Select Register configures the pin driver as Open Drain or CMOS (standard push/pull) for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. Open Drain outputs are diode clamped, thus the maximum voltage on an pin configured as Open Drain is Vcc + 0.7V. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a 1. The default pin drive is CMOS. Note that the slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to 1. The default rate is standard slew. See Appendix A for Drive Register bit definitions. DSP Data Bus. Port F is used for DSP data lines D0-D7 when DSM2150F5V is configured for 8-bit operation. Port G is additionally used for DSP data lines D8-D15 when configured for 16-bit operation. PLD Inputs. Inputs from Ports A, B, and C to the DPLD and CPLD come through IMCs. Inputs from Port D to PLDs are routed directly in and do not use IMCs.
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PLD Outputs. Outputs from the CPLD to Port A come from the OMC group MCELLA0-7. Likewise, Port B is driven by MCELLB0-7. Outputs from the DPLD to Port C come from the external chip select logic block ECS0-7. JTAG In-System Programming (ISP). Some of the pins on Port E implement IEEE 1194.1 JTAG bus for In-System Programming (ISP). You can multiplex the function of these Port E JTAG pins Figure 12. Port A, B and C Structure
DATA OUT Register D WR PORT Pin OUTPUT MUX Q
with other functions. See the section entitled "Programming In-Circuit Using JTAG ISP", and Application Note AN1153. Enable Out. The Enable Out register can be read by the DSP. It contains the output enable values for a given port. A logic 1 indicates the driver is in output mode. A logic 0 indicates the driver is in tristate and the pin is in input mode.
DATA OUT
MCELLA7-MCELLA0 (Port A) MCELLB7-MCELLB0 (Port B) Ext.CS (Port C) READ MUX P D B DATA IN
INTERNAL DATA BUS
ENABLE OUT
DIR Register D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL Q
CPLD - INPUT
AI04936B
Ports A, B and C - Functionality and Structure Ports A and B have similar functionality and structure, as shown in Figure 12. The two ports can be configured to perform one or more of the following functions: s MCU I/O Mode
s
s
DPLD Output - External Chip Select (ECS7ECS0) can be connected to Port C. CPLD Input - Via the Input Macrocells (IMC). Open Drain/Slew Rate - pins PC7-PC0 can be configured to fast slew rate. Pins PA7-PA0, PB7-PB0, and PG7-PB0 and can be configured to Open Drain mode.
s s
CPLD Output - Macrocells McellA7-McellA0 can be connected to Port A. McellB7-McellB0 can be connected to Port B.
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Figure 13. Port D Structure
DATA OUT Register DATA OUT D WR Q
PORT D PIN
INTERNAL DATA BUS
READ MUX
P D B DATA IN
DIR Register D WR Q CPLD - INPUT
AI05774
Port D - Functionality and Structure Port D has four I/O pins. See Figure 13. Port D can be configured to perform one or more of the following functions: s MCU I/O mode
s
s
CLKIN (PD1) as input to the Macrocells Flipflops and APD counter PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. Write High-Byte input (WRH, PD3) used for some 16-bit DSP connections.
s
CPLD Input - direct input to the CPLD, no Input Macrocells (IMC) Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions:
s
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Figure 14. Port E and G Structure
DATA OUT Register D WR Q
PORT Pin DATA OUT
INTERNAL DATA BUS
READ MUX P D B DATA IN
ENABLE OUT
DIR Register D WR ENABLE PRODUCT TERM (.OE) Q
AI05773
Port E - Functionality and Structure Port E can be configured to perform one or more of the following functions (see Figure 14): s MCU I/O Mode
s
In-System Programming (ISP) - JTAG port can be enabled for programming/erase of the PSD device. (See the section entitled "Programming In-Circuit using JTAG ISP", on page 33, for more information on JTAG programming.) Open Drain - pins can be configured in Open Drain Mode
Port F - Functionality and Structure Port F will always be connected to DSP data bus D7-D0. Port G - Functionality and Structure Port G can be configured to perform one or more of the following functions: s Connected to DSP data bus D15-D8 in 16-bit configuration.
s s
MCU I/O Mode in 8-bit configuration. Open Drain - pins can be configured in Open Drain Mode in 8-bit configuration.
s
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POWER MANAGEMENT The device offers configurable power saving options. These options may be used individually or in combinations, as follows: s All memory blocks in the device are built with zero-power technology. Zero-power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an address input, the affected memory "wakes up", changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing--it happens automatically. Both PLDs (DPLD and CPLD) are also Zeropower, but this is not the default operation. The DSP must set a bit at run-time to achieve Zeropower as described. PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories and csiop registers, placing them in standby mode even if address inputs are changing. This feature does not block any internal signals or disable the PLDs. There is a slight penalty in memory access time when PSD Chip Select Input (CSI, PD2) makes its initial transition from deselected to selected.
s
The PMMR registers can be written by the DSP at run-time to manage power. The device has a Turbo bit in the PMMR0 register. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component and the AC component is higher. Further significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. The "blocking bits" in PMMR registers can be set to logic 1 by the DSP to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 16), so blocking unused PLD inputs can significantly lower PLD operating frequency and power consumption. The DSP also has the option of blocking certain PLD inputs when not needed, then letting them pass for when needed for specific logic operations. Table 4 and Appendix A define the PMMR registers.
s
s
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POWER ON RESET, WARM RESET, POWER-DOWN Warm Reset. Once the device is up and running, Power On Reset. Upon Power-up, the device rethe device can be reset with a pulse of a much quires a Reset (RESET) pulse of duration tNLNH-PO shorter duration, tNLNH. The same tOPR period is after VCC is steady. During this time period, the device loads internal configurations, clears some of needed before the device is operational after the registers and sets the Flash memory into Read warm reset. Figure 15 shows the timing of the Array mode. After the rising edge of Reset (REPower-up and warm reset. SET), the device remains in the Reset mode for an I/O Pin, Register and PLD Status at Reset. Taadditional period, t OPR, before the first memory acble 13 shows the I/O pin, register and PLD status cess is allowed. during Power On Reset, warm reset and PowerUpon Power On reset, internal sector selects FS0down mode. PLD outputs are always valid during 7 and CSBOOT0-7 must all be inactive and Write warm reset, and they are valid in Power On Reset Strobe (WR, CNTL0) inactive (logic 1) for maxionce the internal device Configuration bits are mum security of the data contents and to remove loaded. This loading of the device is completed the possibility of a byte/word being written on the typically long before the V CC ramps up to operatfirst edge of Write Strobe (WR, CNTL0). Any Flash ing level. Once the PLD is active, the state of the outputs are determined by the PSDsoft Express memory Write cycle initiation is prevented autoequations. matically when V CC is below VLKO . Figure 15. Reset (RESET) Timing
VCC
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
tOPR
tOPR
RESET
AI02866b
Table 13. Status During Power-On Reset, Warm Reset and Power-down Mode
Port Configuration MCU I/O PLD Output Power-On Reset Input mode Valid after internal PSD configuration bits are loaded (almost immediately) Input mode Valid Warm Reset
Register PMMR0 and PMMR2 OMC Flip-flop status All other registers
Power-On Reset Cleared to 0 Cleared to 0 by internal Power-On Reset Cleared to 0 Unchanged
Warm Reset
Depends on .re and .pr equations Cleared to 0
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PROGRAMMING IN-CIRCUIT USING JTAG ISP In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows programming of the entire DSM device or subsections (i.e. only Flash memory but not the PLDs) without and participation of the DSP. A blank DSM device soldered to a circuit board can be completely programmed in 15to 35 seconds. The basic JTAG signals; TMS, TCK, TDI, and TDO form the IEEE-1149.1 interface. The DSM device does not implement the IEEE-1149.1 Boundary Scan functions. The DSM uses the JTAG interface for ISP only. However, the DSM device can reside in a standard JTAG chain with other JTAG devices as it will remain in BYPASS mode while other devices perform Boundary Scan. ISP programming time can be reduced as much as 30% by using two more signals on Port E, TSTAT and TERR in addition to TMS, TCK, TDI and TDO. See Table 14. The FlashLINKTM JTAG programming cable available from STMicroelectronics for $USD59 and PSDsoft Express software that is available at no charge from www.st.com/psd is all that is needed to program a DSM device using the parallel port on any PC or laptop. By default, the four pins on Port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO on a blank device (and as shipped from factory) See Application Note AN1153 for more details on JTAG In-System Programming (ISP). Standard JTAG Signals. The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are logically ORed. The following symbolic logic equation specifies the conditions enabling the four basic JTAG signals (TMS, TCK, TDI, and TDO) on their respective Port E pins. For purposes of discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are enabled for JTAG operation. When JTAG_ON is false, the four pins can be used for general device I/O as specified in PSDsoft Express. JTAG_ON can become true by any of three different ways as shown: JTAG_ON = 1. PSDsoft Express Pin Configuration -OR2. PSDsoft Express PLD equation -OR3. DSP writes to register in csiop block Method 1 is most common. This is when the JTAG pins are selected in PSDsoft Express to be "dedicated" JTAG pins. They can always transmit and receive JTAG information because they are "fulltime" JTAG pins. Method 2 is used only when the JTAG pins are multiplexed with general I/O functions. For de-
signs that need every I/O pin, the JTAG pins may be used for general I/O when they are not used for ISP. However, when JTAG pins are multiplexed with general I/O functions, the designer must include a way to get the pins back into JTAG mode when it is time for JTAG operations again. In this case, a single PLD input from Ports A, B, C, or D must be dedicated to switch the Port E pins from I/ O mode back to ISP mode at any time. It is recommended to physically connect this dedicated PLD input pin to the JEN\ output signal from the Flashlink cable when multiplexing JTAG signals. See Application Note AN1153 for details. Method 3 is rarely used to control JTAG pin operation. The DSP can set the port E pins to function as JTAG ISP by setting the JTAG Enable bit in a register of the csiop block, but as soon as the DSM chip is reset, the csiop block registers are cleared, which turns off the JTAG-ISP function. Controlling JTAG pins using this method is not recommended. Table 14. JTAG Port Signals
Port E Pin PE0 PE1 PE2 PE3 PE4 PE5 JTAG Signals TMS TCK TDI TDO TSTAT TERR Description Mode Select Clock Serial Data In Serial Data Out Status Error Flag
JTAG Extensions. TSTAT and TERR are two JTAG extension signals (must be used as a pair) enabled by a command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO) by PSDsoft Express. They are used to speed Program and Erase cycles by indicating status on device pins instead of having to scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes Low (active) when an Error condition occurs. TSTAT behaves the same as Ready/Busy described previously. TSTAT is inactive logic 1 when the device is in Read mode (Flash memory contents can be read). TSTAT is logic 0 when Flash memory Program or Erase cycles are in progress. TSTAT and TERR can be configured as opendrain type signals with PSDsoft Express. This facilitates a wired-OR connection of TSTAT signals from multiple DSM2150F5V devices and a wiredOR connection of TERR signals from those same
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devices. This is useful when several devices are "chained" together in a JTAG environment. PSDsoft Express puts TSTAT and TERR signals to open-drain by default. Click on 'Properties' in the JTAG-ISP window of PSDsoft Express to change to standard CMOS push-pull. It is recommended to use 10 k pull-up resistors to VCC on all JTAGISP signals on your circuit board. Initial Delivery State When delivered from ST, the device has all bits in the memory and PLDs erased to logic 1. The DSM Configuration Register bits are set to 0. The code, configuration, and PLD logic are loaded using the programming procedure. The four basic JTAG ISP signals (TCK, TMS, TDI, TDO) are ready for ISP function.
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AC/DC PARAMETERS These tables describe the AC and DC parameters of the device: t DC Electrical Specification t AC Timing Specification s PLD Timing - Combinatorial Timing - Synchronous Clock Mode - Asynchronous Clock Mode - Input MicroCell Timing
s s
s
In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the device is in each mode. Also, the supply power is considerably different if the Turbo bit is 0. The AC power component gives the PLD and Flash memory a mA/MHz specification. Figure 16 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. The fitter report of PSDsoft Express indicates the number of Product Terms (PTs) used for a given design. This number may be used to estimate PLD power consumption using Figure 16. In the PLD timing parameters, add the required delay when Turbo bit is 0.
DSP Timing - Read Timing - Write Timing - Reset Timing
s
The following are issues concerning the parameters presented:
s
Figure 16. PLD ICC /Frequency Consumption (3.3 V)
60 VCC = 3V 50 ICC - (mA) 40
B TUR N( OO 100% )
FF
30
O
TU
20 10
O TURB
RB
ON (2
5%)
O
TU
0 0
RB
5
O
OF
F
PT 100% PT 25%
10
15
20
25
AI03100
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 15. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VPP VESD Storage Temperature Lead Temperature during Soldering (20 seconds max.)1 Input and Output Voltage (Q = VOH or Hi-Z) Supply Voltage Device Programmer Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 -0.6 -0.6 -0.6 -2000 Parameter Min. -65 Max. 125 235 4.0 4.0 14.0 2000 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 16. Operating Conditions
Symbol VCC TA Supply Voltage Ambient Operating Temperature (industrial) Parameter Min. 3.0 -40 Max. 3.6 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 17. AC Measurement Conditions
Symbol CL Load Capacitance Parameter Min. 30 Max. Unit pF
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 17. AC Measurement I/O Waveform
Figure 18. AC Measurement Load Circuit
2.0 V
0.9VCC Test Point 0V
AI04947
400 1.5V Device Under Test
CL = 30 pF (Including Scope and Jig Capacitance)
AI04948
Table 18. Capacitance
Symbol CIN COUT CVPP Parameter Input Capacitance (for input pins) Output Capacitance (for input/ output pins) Capacitance (for CNTL2/VPP) Test Condition VIN = 0V VOUT = 0V VPP = 0V Typ.2 4 8 18 Max. 6 12 25 Unit pF pF pF
Note: 1. Sampled only, not 100% tested. 2. Typical values are for T A = 25C and nominal supply voltages.
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Table 19. AC Symbols for PLD Timing
Signal Letters A C D E N P Q R S W B M Address Input CEout Output Input Data E Input Reset Input or Output Port Signal Output Output Data RD Input (read) Chip Select Input, BMS, DMS, IOMS, or FSx WR Input (write) VSTBY Output Output Macrocell t L H V X Z PW Time Logic Level Low Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width Signal Behavior
Example: tAVWL - Time from Address Valid to Write input Low. Figure 19. Switching Waveforms - Key
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI
WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI
DON'T CARE
CHANGING, STATE UNKNOWN
OUTPUTS ONLY
CENTER LINE IS TRI-STATE
AI03102
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Table 20. DC Characteristics
Symbol VIH VIL VIH1 VIL1 VHYS VLKO Parameter High Level Input Voltage Low Level Input Voltage Conditions 3.0 V < VCC < 3.6 V 3.0 V < VCC < 3.6 V Min. 0.7VCC -0.5 0.8VCC -0.5 0.3 1.5 IOL = 20 A, VCC = 3.0V Output Low Voltage IOL = 4 mA, VCC = 3.0 V IOH = -20 A, VCC = 3.0 V Output High Voltage IOH = -1 mA, VCC = 3.0 V Stand-by Supply Current Input Leakage Current Output Leakage Current CSI >VCC -0.3 V (Note 2,3,4) VSS < VIN < VCC 0.45 < VIN < VCC PLD_TURBO = Off, f = 0 MHz (Note 3) PLD_TURBO = On, f = 0 MHz During Flash memory Write/ Flash memory Erase Only Read Only, f = 0 MHz -1 -10 2.7 2.8 50 .1 5 0 200 10 0 400 25 0 100 1 10 V A A A A/PT A/PT mA mA 2.9 0.15 2.99 0.45 V V 0.01 2.2 0.1 Typ. Max. VCC +0.5 0.8 VCC +0.5 0.2VCC -0.1 Unit V V V V V V V
Reset High Level Input Voltage (Note 1) Reset Low Level Input Voltage Reset Pin Hysteresis VCC (min) for Flash Erase and Program (Note 1)
VOL
VOH
ISTBY ILI ILO
PLD Only ICC (DC) (Note 6) Operating Supply Current
PLD AC Adder ICC (AC) Flash memory AC Adder
(see note 5) 1.5 2.0 mA/ MHz
Note: 1. 2. 3. 4. 5. 6.
Reset has hysteresis. VIL1 is valid at or below 0.2VCC -0.1. VIH1 is valid at or above 0.8VCC . CSI deselected (CSI >VCC -0.3 V) or the DSP is not changing state of any address signal. PLD is in non-Turbo mode, and none of the PLD inputs are switching. No inputs floating, must be solid logic 1 or 0 (pullup to Vcc or gnd, or actively driven) See Figure 16 for the PLD current calculation. IOUT = 0 mA, meaning outputs are driving no loads.
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Table 21. CPLD Combinatorial Timing
-12 Symbol Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Minimum time between switching of any PLD inputs which prevents PLD from entering standby mode. Any MicroCell PLD inputs that switch less frequently than this parameter allow standby PLD mode. 30 27 Add 4 Conditions Min tPD tEA tER tARP tARPW tARD Max 43 45 45 43 PT Aloc Add 4 Turbo Off Add 20 Add 20 Add 20 Add 20 Add 20 Slew Rate1 Sub 6 Sub 6 Sub 6 Sub 6 Unit
ns ns ns ns ns ns
tTURBO
100
ns
Note: 1. Fast Slew Rate output available on Port C and Port F.
Table 22. CPLD MicroCell Synchronous Clock Mode Timing
-12 Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period2 Clock Input Clock Input Clock Input Any MicroCell tCH+tCL 28 Conditions Min 1/(tS+tCO) 1/(tS+tCO-10) 1/(tCH+tCL) 23 0 14 14 26 27 Add 4 Sub 6 Max 20.4 25.6 35.7 Add 4 Add 20 PT Aloc Turbo Off Slew Rate1 Unit
MHz MHz MHz ns ns ns ns ns ns ns
Note: 1. Fast slew rate output available on Port C and Port F. 2. CLKIN (PD1) t CLCL = tCH + tCL.
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Table 23. CPLD MicroCell Asynchronous Clock Mode Timing
-12 Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARD tMINA Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any MicroCell 1/fCNTA 38 Conditions Min 1/(tSA+tCOA) 1/(tSA+tCOA-10) 1/(tCHA+tCLA) 10 12 18 15 38 27 Add 4 Add 20 Add 20 Add 20 Sub 6 Max 20.8 26.3 30.3 Add 4 Add 20 PT Aloc Turbo Off Slew Rate Unit
MHz MHz MHz ns ns ns ns ns ns ns
Figure 20. Input to Output Disable / Enable
INPUT
tER INPUT TO OUTPUT ENABLE/DISABLE
tEA
AI02863
Figure 21. Asynchronous Reset / Preset
tARPW
RESET/PRESET INPUT tARP REGISTER OUTPUT
AI02864
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Figure 22. Synchronous Clock Mode Timing - PLD
tCH tCL
CLKIN
tS INPUT
tH
tCO REGISTERED OUTPUT
Figure 23. Asynchronous Clock Mode Timing (product term clock)
tCHA tCLA
CLOCK
tSA
tHA
INPUT tCOA REGISTERED OUTPUT
AI02859
Table 24. Input MicroCell Timing
-12 Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions Min (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) 0 23 13 13 62 Add 4 Add 20 Add 20 Max PT Aloc Turbo Off Unit ns ns ns ns ns
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD.
Figure 24. Input MicroCell Timing (product term clock)
t INH
PT CLOCK
t INL
t IS
INPUT
t IH
OUTPUT
t INO
AI03101
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Table 25. Read Timing
-12 Symbol tAVQV tSLQV tRLQV tRHQX tRLRH tRHQZ Parameter Address Valid to Data Valid CS Valid to Data Valid RD to Data Valid 8-Bit Bus RD Data Hold Time RD Pulse Width RD to Data High-Z 1 40 20 Conditions Min (Note 1) Max 120 120 35 Turbo Off Add 20 Unit ns ns ns ns ns ns
Note: 1. Any input used to select an internal DSM function.
Figure 25. Read Timing
tAVQV ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLQV CSI tRLQV tRLRH RD tRHQZ tRHQX ADDRESS VALID
DATA VALID
AI04908
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Table 26. Write Timing
-12 Symbol tAVWL tSLWL tDVWH tWHDX_8 tWHDX_16 tWLWH tWHAX1 tWHAX2 tWHPV tDVMV tWLMV
Note: 1. 2. 3. 4. 5.
Parameter Address Valid to Leading Edge of WR CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time for 8-bit mode WR Data Hold Time for 16-bit mode WR Pulse Width Trailing Edge of WR to Address Invalid Trailing Edge of WR to DPLD Address Invalid Trailing Edge of WR to Port Output Valid Using I/O Port Data Register Data Valid to Port Output Valid Using MicroCell Register Preset/Clear WR Valid to Port Output Valid Using MicroCell Register Preset/Clear
Conditions Min (Note 1) 8 8 45 5 (Note 5) 8 45 1.75 (Note4) 0 33 (Note 3) (Note 2) 68 70 Max
Unit ns ns ns ns ns ns ns ns ns ns ns
Any input used to select an internal PSM function. Assuming data is stable before active write signal. Assuming write is active before data becomes valid. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal DSM memory. tWHAX_16 is 11 ns when writing to the Output Microcells
Figure 26. Write Timing
tAVWL ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLWL CSI tDVWH WR t WLWH t WHDX t WHAX ADDRESS VALID DATA VALID
AI04909
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Table 27. Flash Memory Program, Write and Erase Times
Symbol Parameter Flash Bulk Erase1 (pre-programmed) Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) tTIMEOUT tQ7VQV tTIMOUT Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2 Toggle Flag toggles after Suspend Sector Erase Instruction 0.1 100,000 80 30 15 Min. Typ. 3 10 1 2.2 14 1200 30 Max. 30 Unit s s s s s cycles s ns s
Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Figure 27. Reset (RESET) Timing
VCC
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
tOPR
tOPR
RESET
AI02866b
Table 28. Reset (Reset) Timing
Symbol tNLNH tNLNH-PO tNLNH-A tOPR Parameter RESET Active Low Time 1 Power On Reset Active Low Time Warm Reset Active Low time 2 RESET High to Operational Device Flash memory returns to read mode after Flash Reset Intruction If Flash Program, Erase, or Error condition was in progress Conditions Min 300 1 25 300 Max Unit ns ms us ns us
tREAD_ARRAY
25
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode.
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Table 29. ISC Timing
-12 Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions Min (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 12 5 32 32 32 40 40 2 Max 12 MHz ns ns MHz ns ns ns ns ns ns ns Unit
Note: 1. For non-PLD Programming, Erase or in by-pass mode. 2. For Program or Erase PLD only.
Figure 28. ISC Timing
t ISCCH
TCK
t ISCCL t ISCPSU t ISCPH
TDI/TMS
t ISCPZV t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
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PACKAGE MECHANICAL TQFP80 - 80 lead Plastic Quad Flatpack
D D1 D2 A2
e Ne E2 E1 E b
N 1
Nd L1
A CP
c
QFP-A
A1
L
Note: Drawing is not to scale.
TQFP80 - 80 lead Plastic Quad Flatpack
Symb. A A1 A2 b c D D1 D2 E E1 E2 e L L1 CP N Nd Ne 14.000 12.000 9.500 14.000 12.000 9.500 0.500 0.600 1.000 0.080 80 20 20 -- -- 0.450 -- -- 0.750 -- -- 3.5 0.220 0.050 0.950 0.0 0.170 0.090 mm Typ. Min. Max. 1.200 0.150 1.050 7.0 0.270 0.200 0.5512 0.4724 0.3740 0.5512 0.4724 0.3740 0.0197 0.0236 0.0394 0.0031 80 20 20 -- -- 0.0177 -- -- 0.0295 -- -- 3.5 0.0087 0.0020 0.0374 0.0 0.0067 0.0035 Typ. inches Min. Max. 0.0472 0.0059 0.0413 7.0 0.0106 0.0079
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DSM2150F5V
Table 30. Pin Assignments - TQFP80
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Assign ments PD2 PD3 AD0 AD1 AD2 AD3 AD4 GND VCC AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Assign ments PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 VCC GND PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 RESET CNTL2 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Assign ments PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0 CNTL1 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Assign ments PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VCC GND PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PD0 PD1
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PART NUMBERING Table 31. Ordering Information Scheme
Example: DSM21 50 F5 V - 12 T 6
Device Type DSM21=DSP System Memory for ADSP-21XXX Famly DSM Series 50 = 4.25M bit, Dual Array Flash, 40 I/O
Main Flash Memory Density F5 = 4Mbit
Operating Voltage (Vcc) V = 3.3V 10% Access Time 12 = 120 nsec Package T = 80-pin TQFP
Temperature Range 6 = -40 to 85oC (Industrial)
For a list of available options (speed, package, etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
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APPENDIX A. CSIOP REGISTER BIT DEFINITIONS Table 32. Data-In Registers - Ports A, B, C, D, E, G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions (Read-only registers): Read Port pin status when Port is in MCU I/O input mode.
Table 33. Data-Out Registers - Ports A, B, C, D, E, G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 34. Direction Registers - Ports A, B, C, D, E, G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Port pin 0 = Port pin is configured in Input mode (default). Port pin 1 = Port pin is configured in Output mode.
Table 35. Drive Registers - Ports A, B, E, G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured for Open Drain output driver.
Table 36. Drive Registers - Port C
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured in Slew Rate mode.
Table 37. Enable-Out Registers - Ports A, B, C
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions (Read-only registers): Port pin 0 = Port pin is in tri-state driver (default). Port pin 1 = Port pin is enabled.
Table 38. Input Macrocells - Ports A, B, C
Bit 7 IMcell 7 Bit 6 IMcell 6 Bit 5 IMcell 5 Bit 4 IMcell 4 Bit 3 IMcell 3 Bit 2 IMcell 2 Bit 1 IMcell 1 Bit 0 IMcell 0
Note: Bit Definitions (Read-only registers): Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
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Table 39. Output Macrocells A Register
Bit 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
Note: Bit Definitions: Write Register: Load MCellA7-MCellA0 with 0 or 1. Read Register: Read MCellA7-MCellA0 output status.
Table 40. Output Macrocells B Register
Bit 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
Note: Bit Definitions: Write Register: Load MCellB7-MCellB0 with 0 or 1. Read Register: Read MCellB7-MCellB0 output status.
Table 41. Mask Macrocells A Register
Bit 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
Note: Bit Definitions: McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default). McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by DSP.
Table 42. Mask Macrocells B Register
Bit 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
Note: Bit Definitions: McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default). McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by DSP.
Table 43. Flash Memory Protection Register
Bit 7 Sec7_Prot Bit 6 Sec6_Prot Bit 5 Sec5_Prot Bit 4 Sec4_Prot Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot
Note: Bit Definitions (Read-only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected.
Table 44. Flash Boot Protection Register
Bit 7 Security_Bit Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot
Note: Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set.
Table 45. JTAG Enable Register
Bit 7 not used Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 not used Bit 1 not used Bit 0 JTAGEnable
Note: Bit Definitions: JTAGEnable 1 = JTAG Port is enabled. JTAGEnable 0 = JTAG Port is disabled.
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Table 46. Page Register
Bit 7 PGR 7 Bit 6 PGR 6 Bit 5 PGR 5 Bit 4 PGR 4 Bit 3 PGR 3 Bit 2 PGR 2 Bit 1 PGR 1 Bit 0 PGR 0
Note: Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0=0.
Table 47. PMMR0 Register
Bit 7 not used (set to 0) Bit 6 not used (set to 0) Bit 5 PLD MCells CLK Bit 4 PLD Array CLK Bit 3 PLD Turbo Bit 2 not used (set to 0) Bit 1 not used (set to 0) Bit 0 not used (set to 0)
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers. Note: Bit Definitions: PLD Turbo 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 48. PMMR2 Register
Bit 7 not used (set to 0) Bit 6 PLD Array WRH Bit 5 not used (set to 0) Bit 4 PLD Array CNTL2 Bit 3 PLD Array CNTL1 Bit 2 PLD Array CNTL0 Bit 1 not used (set to 0) Bit 0 PLD Array Addr
Note: For Bit 4, Bit 3, Bit 2: See Table 47 for the signals that are blocked on pins CNTL0-CNTL2. Note: Bit Definitions: PLD Array Addr 0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array WRH 0 = WRH input to the PLD AND array is connected. 1 = WRH input to the PLD AND array is disconnected, saving power.
Table 49. Memory_ID0 Register
Bit 7 not used (set to 0) Bit 6 not used (set to 0) Bit 5 not used (set to 0) Bit 4 not used (set to 0) Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0
Note: Bit Definitions: F_size[3:0]
5h = Primary Flash memory size is 4 Mbit 6h = Primary Flash memory size is 8 Mbit
Table 50. Memory_ID1 Register
Bit 7 not used (set to 0) Bit 6 not used (set to 0) Bit 5 not used (set to 0) Bit 4 not used (set to 0) Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0
Note: Bit Definitions: B_size[3:0]
2h = Secondary NVM size is 256 Kbit 3h = Secondary NVM size is 512 Kbit
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ADSP-21535 BlackFin DSM2150F5V
INTERRUPT PLL BYPASS CLOCK OUT
NMI BYPASS CLKOUT CLKIN1 XTALI XTALO 16 PF15-0 DATA7-DATA0 DATA15-DATA8 8 DATA 8 DATA PF7-PF0 PG7-PG0
NO CONNECT
WRITE READ BYTE SELECT 1 MEM SELECT 0
CNTL0 (_wr) CNTL1 (_rd) CNTL2 (_bhe) PC6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
OSC RTC XTAL 32.768KHz
_AWE _AOE _ABE1 _AMS0 _AMS1 _AMS2 _AMS3 _ABE2 _ARE ARDY
GPIO/INTR/ SPI I/O SEL 6 SPORT0 32K Byte x 16 Flash Mem 16 Cell PLD 512K Byte x 16 Flash Mem
SERIAL DEVICE 6
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
SERIAL DEVICE 3
SPI SERIAL DEVICE 3
PC7 PD0 PD1 PD3 PE4 PE5 PE6 PE7
I/O I/O I/O I/O I/O I/O I/O I/O
VCC
SPI SERIAL DEVICE 2
10k optional TSTAT optional _TERR 33 TMS TCK TDI TDO
UART DEVICE 2
SLEEP _RESET
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21
PWM/TIMER/ CAPTURE TMR2-0 BMODE0 BMODE1 BMODE2 8 USB
3
TMS TCK TDI TDO _RESET
USB DEVICE(s) 54 PCI
TDI TDO TCK TMS _TRST _EMU
OPTIONALLY COMBINE JTAG CONNECTORS AND CHAIN DEVICES 33
DSM JTAG CONNECTOR PD2 (_csi) _RESET PE0 PE1 PE2 PE3
JTAG TDI JTAG TDO JTAG TCK JTAG TMS JTAG _TRST EMULATOR STATUS
Figure 29. Typical Connections, DSM2150F5V and ADSP-21535 Blackfin DSP
UART DEVICE
_ABE0 (ADDR0) _ABE3 (ADDR1) ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 SPORT1 ADDR7 ADDR8 ADDR9 ADDR10 SPI0 ADDR11 ADDR12 ADDR13 ADDR14 SPI1 ADDR15 ADDR16 ADDR17 ADDR18 UART0 (IrDA) ADDR19 ADDR20 ADDR21 UART1 SLEEP _RESET A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 PC0 PC1 PC2 PC3 PC4 PC5
PCI BUS
DSP JTAG CONNECTOR
APPENDIX B. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-21535 BLACKFIN DSP
SDRAM
SYNC MEM
DSM2150F5V
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DSM2150F5V
Typical Memory Map, DSM2150F5V and ADSP21535 BLACKFIN DSP There many different ways to place (or map) the addresses of DSM memory and I/O depending on system requirements. The DPLD allows complete mapping flexibility. Figure 30 shows one possible system memory map. In this example, the DSP will bypass it's internal boot ROM at power-on and begin executing code directly from the DSM2150F5V secondary Flash memory. While executing this code, the DSP will load the contents of the DSM2150F5V main Flash memory into the ADSP-21535 internal SRAM, then execute code from that high performance SRAM. The advantage of this is speed, flexibility, IAP, clean software partitioning, and parameter storage. - Loading external Flash memory to internal SRAM by 16-bits is faster than booting by 8bits. Also, subsequent loading of new memory overlays during runtime is also faster by 16-bits. - Bypassing internal DSP boot ROM and executing from DSM secondary memory provides total flexibility to meet system requirements. Like having custom boot ROM programmable by JTAG. - In-Application Programming (IAP) can be implemented by placing custom loader code in DSM secondary flash which, when executed, allows the DSP to receive data over any communication channel (i.e. USB) and write new code/data the DSM main flash memory. Since the DSM Flash arrays are independent, it is possible to read from the secondary flash while writing to the main Flash. - Since the DSM secondary Flash has smaller sector sizes, small data sets and calibration constants may be stored there. EEPROM emulation techniques can be used. - Placing start-up and IAP code in DSM secondary Flash keeps it totally separate DSM main flash memory, affording clean software partitioning. This also ensures robust system operaton since start-up code will always be there and removed from accitental writes or erasures of DSM main flash. The nomenclature fs0..fs7 in Figure 30 are designators for the individual sectors of Main Flash memory, 64 KBytes each. csboot0..csboot3 are designators for the individual Secondary Flash memory segments, 8 KBytes each. csiop designates the DSM control register block. The designer may easily specify memory mapping in a point-and-click software environment using PSDsoft ExpressTM. Figure 30. Memory Map, ADSP-21535
9FFFF
fs7 64K bytes Main Flash
90000 8FFFF
fs6 64K bytes Main Flash
80000 7FFFF
fs5 64K bytes Main Flash
70000 6FFFF
fs4 64K bytes Main Flash
60000 5FFFF
fs3 64K bytes Main Flash
50000 4FFFF
fs2 64K bytes Main Flash
40000 3FFFF
fs1 64K bytes Main Flash
30000 2FFFF
fs0 64K bytes Main Flash
20000 Nothing Mapped 10000-100FF
csiop, Control Regs
Nothing Mapped 06000-07FFF 04000-05FFF 02000-03FFF 00000-01FFF
csboot, 8KB 2nd Flash csboot, 8KB 2nd Flash csboot, 8KB 2nd Flash csboot, 8KB 2nd Flash
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Specifying the Memory Map with PSDsoft ExpressTM The memory map shown in Figure 30 can be easily implemented using PSDsoft ExpressTM in a point-and-click environment. PSDsoft Express TM will generate Hardware Definition Language (HDL) statements of the ABEL language. Figure 31 shows the resulting equations generated by PSDsoft ExpressTM.
Figure 31. HDL Statements Generated from PSDsoft Express to Implement Memory Map csiop = ((address >= ^h10000) & (address <= ^h100FF) & (!_ams0)); fs0 = ((address >= ^h20000) & (address <= ^h2FFFF) & (!_ams0)); fs1 = ((address >= ^h30000) & (address <= ^h3FFFF) & (!_ams0)); fs2 = ((address >= ^h40000) & (address <= ^h4FFFF) & (!_ams0)); fs3 = ((address >= ^h50000) & (address <= ^h5FFFF) & (!_ams0)); fs4 = ((address >= ^h60000) & (address <= ^h6FFFF) & (!_ams0)); fs5 = ((address >= ^h70000) & (address <= ^h7FFFF) & (!_ams0)); fs6 = ((address >= ^h80000) & (address <= ^h8FFFF) & (!_ams0)); fs7 = ((address >= ^h90000) & (address <= ^h9FFFF) & (!_ams0)); csboot0 = ((address >= ^h0000) & (address <= ^h1FFF) & (!_ams0)); csboot1 = ((address >= ^h2000) & (address <= ^h3FFF) & (!_ams0)); csboot2 = ((address >= ^h4000) & (address <= ^h5FFF) & (!_ams0)); csboot3 = ((address >= ^h6000) & (address <= ^h7FFF) & (!_ams0)); Specifying these equations using PSDsoft ExpressTM is very simple. Figure 32 shows how to specify the equation for the 64 KByte Flash memory segment, fs0. Notice fs0 is qualified with the Figure 32. PSDsoft ExpressTM Memory Mapping signal AMS0. This specification process is repeated for all other Flash memory segments, the csiop register block, and any external chip select signals that may be needed.
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SERIAL DEVICE SPORT1 EBOOT LBOOT _RESET
_RESET
TMS TCK TDI TDO _RESET
Figure 33. Typical Connections, DSM2150F5V and ADSP-21062 Sharc DSP
HOST
HOST INTERFACE DMA CONTROL
TDI TDO TCK TMS _TRST _EMU
OPTIONALLY COMBINE JTAG CONNECTORS AND CHAIN DEVICES 33 JTAG TDI JTAG TDO JTAG TCK JTAG TMS JTAG _TRST EMULATOR STATUS
PERIPHERAL
DSP JTAG CONNECTOR
APPENDIX C. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-21062 SHARC DSP
SHARC
DSM JTAG CONNECTOR
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ADSP-21062L SHARC DSP DSM2150F5V
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O TIMER OUT
DSM2150F5V
TIMEXP 3 IRQ2-0 512K Byte x 8 Flash Mem 32K Byte x 8 Flash Mem 16 Cell PLD 8 DATA PF7-PF0 PD0 PD1 PD2 PD3 PC6 PC7
PLD & I/O PLD & I/O
WRITE READ BOOT MEM SELECT
CNTL0 (_wr) CNTL1 (_rd) CNTL2
INTERRUPT SOURCES CLOCK CIRCUITRY CLOCKS 4 FLAG3-0 GPIO 6
_WR _RD _BMS _WRH _MS3-0 ACK DATA47-DATA8 ADDR31-ADDR22 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
PERIPHERAL 6 LINK PORT 1
DATA23-DATA16 LINK PORT 0
I/O I/O I/O I/O
PERIPHERAL 6 LINK PORT 2
PERIPHERAL 6 LINK PORT 3
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
I/O I/O I/O I/O I/O I/O I/O I/O
PERIPHERAL 6 LINK PORT 4
VCC
PERIPHERAL 6 LINK PORT 5
PD0 PD1 PD2 PD3 PE4 PE5 PE6 PE7
I/O I/O I/O I/O I/O I/O I/O I/O
10k optional TSTAT optional _TERR TMS TCK TDI TDO 33
PERIPHERAL 6 SPORT0 SERIAL DEVICE 6
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 PC0 PC1 PC2 PC3 PC4 PC5 _RESET PE0 PE1 PE2 PE3
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21
ADSP-TS101S TigerSHARC
DSM2150F5V
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
WRITE LOW BYTE READ BOOT MEM SELECT
CNTL0 (_wr) CNTL1 (_rd) CNTL2 512K Byte x 8 Flash Mem 32K Byte x 8 Flash Mem
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
TIMER OUT
INTERRUPT SOURCES CLOCK CIRCUITRY CLOCKS 16 Cell PLD DATA7-DATA0 8 DATA PF7-PF0 4 FLAG3-0 GPIO 11 LINK PORT 0 PD0 PD1 PD2 PD3
I/O I/O I/O I/O
4
PLD & I/O PLD & I/O
_WRL _RD _BMS _WRH _MS0 _TMROE _MS1 DATA63-DATA8 ADDR31-ADDR22 _INTR3-0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC6 PC7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
PERIPHERAL 11 LINK PORT 1
PERIPHERAL 11 LINK PORT 2
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
I/O I/O I/O I/O I/O I/O I/O I/O
PERIPHERAL 11 LINK PORT 3
VCC
PERIPHERAL
PD0 PD1 PD2 PD3 PE4 PE5 PE6 PE7
I/O I/O I/O I/O I/O I/O I/O I/O
10k optional TSTAT optional _TERR TMS TCK TDI TDO 33
HOST
HOST INTERFACE SYNC MEM
SDRAM
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 PC0 PC1 PC2 PC3 PC4 PC5 _RESET PE0 PE1 PE2 PE3 _RESET EBOOT
_RESET
Figure 34. Typical Connections for ADSP-TS101S TigerSHARC DSP
PERIPHERAL
DMA CONTROL
TMS TCK TDI TDO _RESET
OPTIONALLY COMBINE JTAG CONNECTORS AND CHAIN DEVICES 33 TDI TDO TCK TMS _TRST _EMU JTAG TDI JTAG TDO JTAG TCK JTAG TMS JTAG _TRST EMULATOR STATUS
DSP JTAG CONNECTOR
DSM JTAG CONNECTOR
APPENDIX D. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-TS101S TIGERSHARC DSP
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21
DSM2150F5V
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TMS TCK TDI TDO _RESET
TIMER/ CAPTURE TMR2-0
BMODE0 BMODE1 OPMODE
OPTIONALLY COMBINE JTAG CONNECTORS AND CHAIN DEVICES 33 JTAG TDI JTAG TDO JTAG TCK JTAG TMS JTAG _TRST EMULATOR STATUS
HOST PORT Hx
TDI TDO TCK TMS _TRST _EMU
DSP JTAG CONNECTOR
DSM JTAG CONNECTOR
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ADSP-2191M
512K Byte x 8 Flash Mem _BR _BG _BGH 32K Byte x 8 Flash Mem 16 Cell PLD BYPASS CLKOUT CLKIN XTAL PC0 PC1 PC2 PC3 PD2 PD3 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O _WR _RD _BMS _IOMS _MSx ACK WRITE READ BOOT MEM SELECT I/O MEM SELECT MEM SELECT
DSM2150F5V
DSM2150F5V
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
BUS_REQUEST BUS_GRANT GRANT_HUNG
PLL BYPASS CLOCK OUT
CLOCK or XTAL CNTL0 (_wr) CNTL1 (_rd) CNTL2 PD0 PD1
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 DATA7-DATA0 8 DATA PF7-PF0 SPORT0 SERIAL CHN SPORT1 SERIAL CHN SPORT2 SERIAL or (2) SPI RxD, TxD _RESET
RESET VCC
SERIAL DEVICE PE4 PE5 PE6 PE7
I/O I/O I/O I/O
SERIAL DEVICE
10k optional TSTAT optional _TERR 33
Figure 35. Typical Connections, DSM2150F5V and ADSP-2191M
SERIAL SPI DEVICE _RESET
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
TMS TCK TDI TDO
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 PC4 PC5 PC6 PC7
APPENDIX E. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-2191 Note: DSP HCLK is limited to 45 MHz to satisfy the Write Hold Enable (E_WHE) memory space DSM2150F5V parameter, tAVWL. If HCLK is greatsetting of the ADSP-2191 must be set to hold the er than 45 MHz, a non-inverting buffer should be DSP address after the delayed rising edge of WR. placed between WR signal output from ADSP219x and CNTL0 input to DSM2150. This delays the falling edge of WR to satisfy t AVWL, However,
UART DEVICE
PE0 PE1 PE2 PE3
DSM2150F5V
512K Byte x 8 Flash Mem 32K Byte x 8 Flash Mem 16 Cell PLD
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
BUS_REQUEST BUS_GRANT GRANT_HUNG
ADSP-2188M
_BR _BG _BGH _PWD CLKIN XTAL
N/C N/C WRITE READ BYTE MEM SELECT I/O MEM SELECT DATA MEM SELECT
PWR_DOWN_IN
CLOCK or XTAL PC0 PC1 PC2 PC3 PD3 PF7-PF0 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
PLD & I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
_WR _RD _BMS _IOMS _DMS _PMS _CMS PLD & I/O PLD & I/O PLD & I/O PLD & I/O
CNTL0 (_wr) CNTL1 (_rd) CNTL2 PD0 PD1
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O PLD & I/O
FL0 FL1 FL2 DATA15-DATA8 8 DATA (Upper byte) PF0/MODEA PF1/MODEB PF2/MOCEC PF3 _IRQE/PF4 _IRQL0/PF5 _IRQL1/PF6 _IRQ2/PF7
I/O I/O I/O I/O INTR/I_O INTR/I_O INTR/I_O INTR/I_O
Figure 36. Typical Connections, DSM2150F5V and ADSP-2188M
VCC
SERIAL DEVICE SERIAL DEVICE
POWER DOWN _RESET
SPORT0 SERIAL CHN SPORT1 SERIAL CHN DEBUG PWDACK _RESET
PE4 PE5 PE6 PE7
I/O I/O I/O I/O
10k optional TSTAT optional _TERR
APPENDIX F. TYPICAL CONNECTIONS, DSM2150F5V AND ADSP-2188M
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 D16 D17 D18 D19 D20 D21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 PC4 PC5 PC6 PC7 PD2 (_CSI) _RESET
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19
33
TMS TCK TDI TDO _RESET
DSM JTAG CONNECTOR
PE0 PE1 PE2 PE3
TMS TCK TDI TDO
ICE-Port
DSM2150F5V
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REVISION HISTORY Table 51. Document Revision History
Date 14-Feb-2002 Rev. 1.0 Document written Description of Revision
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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